RE: The custom device tree pins conflict with the default GPIO pins.

Kazi Afroza Sultana — Fri, 17 Oct 2025 12:57:19 GMT

Hello,

I have looked at your overlay file.

There are few things described below, you must consider reviewing the design again.

a. P0.13 to P0.18 are used as quad SPI using the direct connection of the QSPI peripheral.

These pins must be enabled using the Peripheral option of the PIN_CNF register. For high-speed SPI (SPIM4), a different set of dedicated pins (P0.08–P0.12) is used, and when activated, the SPIM PSEL settings are ignored, and the dedicated pins are used.'

The documentation explicitly separates the use of QSPI and SPIM4 dedicated pins and does not recommend cross-usage between these functions. In this way, we can ensure is to ensure proper operation and signal integrity at high speeds Pin assignments and special GPIO considerations.

I can see in your overlay file, you have used some of these QSPI pins of SPIM.

b. Same for UART_RX pin, you have setP0.00 as UART_RX pin; which is used as Analog input for 32kHz crystal.

If you want to use P0.00 as UART_RX (or any other GPIO function), you must (32.768 kHz crystal):

Disconnect the 32.768 kHz crystal from P0.00 by cutting the appropriate solder bridge (SB2) and
Connect P0.00 to the GPIO header by soldering the corresponding bridge (SB4).

c. You have used P1.03 for MOSI pin. Usually, P1.02 and P1.03 are used as high speed TWIM.

However, it is also used as GPIO pin.

So, you can use it for SPI pin as long as you don't need this for TWI.

Thanks.

Kazi