How do I adjust the PDM clock frequency and PDMCLKCTRL register value of the nRF5340?

RE: How do I adjust the PDM clock frequency and PDMCLKCTRL register value of the nRF5340?

Kevin Lin — Tue, 03 Feb 2026 09:49:46 GMT

Hi Håkon,

No problem at all. Thank you, and have a great day as well!

Best regards,

Kevin

RE: How do I adjust the PDM clock frequency and PDMCLKCTRL register value of the nRF5340?

Håkon Alseth — Tue, 03 Feb 2026 09:16:45 GMT

Hi Kevin,

Nothing to apologise for. Please feel free to contact us if anything else should pop up.

I wish you a great day!

Kind regards,

Håkon

RE: How do I adjust the PDM clock frequency and PDMCLKCTRL register value of the nRF5340?

Kevin Lin — Tue, 03 Feb 2026 02:32:39 GMT

Hi Håkon,

Sincere apologies for the delayed response. I no longer need this at this stage. Thank you for your help.

Best regards,

Kevin

RE: How do I adjust the PDM clock frequency and PDMCLKCTRL register value of the nRF5340?

Håkon Alseth — Tue, 06 Jan 2026 15:51:43 GMT

Hi Kevin,

My apologies for the late reply. I have been out of the office.

[quote user="Kevin6_Lin"]

The nRF5340's PDM clock frequency range is between 1MHz and 1.333MHz. Therefore, based on the PDM clock frequency range limitation, I currently plan to adjust the PDM clock frequency to 1.28MHz to meet the microphone's normal mode frequency range for initial testing.

[/quote]

This sounds reasonable.

[quote user="Kevin6_Lin"]Based on my previous test following your suggested modifications, I found that the microphone couldn't record any sound (currently, I'm only testing with human voices).[/quote]

Was there any errors or issues reported over the console?

Did you check if there was any output on the GPIOs that you chose?

It a bit unclear to me if everything worked as expected when you had a wider frequency range set. Could you clarify this?

Kind regards,

Håkon

RE: How do I adjust the PDM clock frequency and PDMCLKCTRL register value of the nRF5340?

Kevin Lin — Tue, 23 Dec 2025 03:26:04 GMT

Hi Håkon,

Sorry, I'm not very familiar with PDM and my explanation may not be clear enough.

My project uses the nRF5340 as the SoC, which connects to the Infineon IM69D128SV01 microphone via a PDM interface.

Based on the clock frequency range specified in section 4.2 Electrical parameters of the IM69D128SV01 datasheet, the low-power mode range is between 380kHz and 1020kHz, and the normal mode range is between 1.2MHz and 3.3MHz.

IM69D128SV01 datasheet: https://www.infineon.com/assets/row/public/documents/24/49/infineon-im69d128s-datasheet-en.pdf?fileId=8ac78c8c85c5e5aa0185dfa527036dad

nRF5340 datasheet: https://docs-be.nordicsemi.com/bundle/ps_nrf5340/page/nRF5340_PS_v1.6.pdf?_LANG=enus

Based on my previous test following your suggested modifications, I found that the microphone couldn't record any sound (currently, I'm only testing with human voices).

I suspect it's because I both set the minimum and maximum frequencies of the "cfg" variable to 1.28MHz, causing the microphone to only record sound at that frequency.

However, this isn't the result I want. I want to be able to record real-life sounds (mostly human voices) with the PDM clock frequency at 1.28MHz.

By the way, I found the APIs "nrf_pdm_clock_set()" and "nrf_pdm_ratio_set()" online. It's "possibly" possible to set the PDM clock frequency to 1.28MHz using "nrf_pdm_clock_set()" via "NRF_PDM_FREQ_1280K". I'm not sure about the purpose of "nrf_pdm_ratio_set()".

However, I've tested this version, and it still can't record any sound. Is my modification correct and effective? If not, is there any way to achieve this through code?

nrf5340_cpuapp_common.dtsi

dmic: &pdm0 {
	status = "okay";
	pinctrl-0 = <&pdm0_default_alt>;
	pinctrl-1 = <&pdm0_sleep>;
	pinctrl-names = "default", "sleep";
	clock-source = "PCLK32M";
	queue-size = <192>;
	zephyr,pm-device-runtime-auto;
};

// &clock {
// 	hfclkaudio-frequency = <11288000>;
// };

dmic.c

#define MAX_SAMPLE_RATE  16000
#define SAMPLE_BIT_WIDTH 16
#define BYTES_PER_SAMPLE sizeof(int16_t)
/* Milliseconds to wait for a block to be read. */
#define READ_TIMEOUT     110

/* Size of a block for 50 ms of audio data. */
#define BLOCK_SIZE(_sample_rate, _number_of_channels) \
	(BYTES_PER_SAMPLE * (_sample_rate / 20) * _number_of_channels)

/* Driver will allocate blocks from this slab to receive audio data into them.
 * Application, after getting a given block from the driver and processing its
 * data, needs to free that block.
 */
#define MAX_BLOCK_SIZE   BLOCK_SIZE(MAX_SAMPLE_RATE, 1)

static const struct device *const DMIC = DEVICE_DT_GET(DT_NODELABEL(dmic));

int dmic_init(void)
{
    int ret = -1;
    if (!device_is_ready(DMIC)) {
        LOG_ERR("%s is not ready", DMIC->name);
        return -1;
    }

    struct pcm_stream_cfg stream = { .pcm_width = SAMPLE_BIT_WIDTH,
                                     .mem_slab = &mem_slab,
                                     .block_size = MAX_BLOCK_SIZE,
                                     .pcm_rate = 16000 };
    struct dmic_cfg cfg = {
      .io =
          {
              /* These fields can be used to limit the PDM clock
               * configurations that the driver is allowed to use
               * to those supported by the microphone.
               */
              .min_pdm_clk_freq = 450000,
              .max_pdm_clk_freq = 3300000,
              .min_pdm_clk_dc = 45,
              .max_pdm_clk_dc = 55,
          },
      .streams = &stream,
      .channel =
          {
              .req_num_streams = 1,
          },
  };

    cfg.channel.req_num_chan = 1;
    cfg.channel.req_chan_map_lo = dmic_build_channel_map(0, 0, PDM_CHAN_LEFT);
    cfg.streams[0].pcm_rate = MAX_SAMPLE_RATE;
    cfg.streams[0].block_size =
        BLOCK_SIZE(cfg.streams[0].pcm_rate, cfg.channel.req_num_chan);

    LOG_INF(
        "PCM output rate: %u, channels: %u",
        cfg.streams[0].pcm_rate,
        cfg.channel.req_num_chan);

    ret = dmic_configure(DMIC, &cfg);
    if (ret < 0) {
        LOG_ERR("Failed to configure the driver: %d", ret);
    }

    /* Force PDMCLKCTRL to 1280K => 1.280 MHz */
    nrf_pdm_clock_set(NRF_PDM0, NRF_PDM_FREQ_1280K);

    /* Optional: choose RATIO=80 to get 16 kHz from 1.28 MHz */
    nrf_pdm_ratio_set(NRF_PDM0, NRF_PDM_RATIO_80X);

    nrf_pdm_gain_set(NRF_PDM0, NRF_PDM_GAIN_MAXIMUM, NRF_PDM_GAIN_MAXIMUM);
    nrf_pdm_gain_t l_gain = 0;
    nrf_pdm_gain_t r_gain = 0;
    nrf_pdm_gain_get(NRF_PDM0, &l_gain, &r_gain);

    LOG_INF(
        " nrfx_clock_hfclkaudio_config_get = %d",
        nrfx_clock_hfclkaudio_config_get());
    LOG_INF("PDM gain = %d", l_gain);
    return 0;
}

Thank you very much for your explanation and help.

Best regards,

Kevin

RE: How do I adjust the PDM clock frequency and PDMCLKCTRL register value of the nRF5340?

Håkon Alseth — Fri, 19 Dec 2025 13:43:59 GMT

Hi,

You are hard-coding it to that specific frequency, with no variance. If this is what you want, then that is OK.

Are you seeing any issues when running this configuration towards your external device?

Kind regards,

Håkon

RE: How do I adjust the PDM clock frequency and PDMCLKCTRL register value of the nRF5340?

Kevin Lin — Fri, 19 Dec 2025 09:22:43 GMT

Hi Håkon,

Below is a portion of my project's code, not the DMIC example.

Is it correct to modify my code as shown below?

nrf5340_cpuapp_common.dtsi

dmic: &pdm0 {
	status = "okay";
	pinctrl-0 = <&pdm0_default_alt>;
	pinctrl-1 = <&pdm0_sleep>;
	pinctrl-names = "default", "sleep";
	clock-source = "PCLK32M";
	queue-size = <192>;
	zephyr,pm-device-runtime-auto;
};

// &clock {
// 	hfclkaudio-frequency = <11288000>;
// };

dmic.c

struct dmic_cfg cfg = {
      .io =
          {
              /* These fields can be used to limit the PDM clock
               * configurations that the driver is allowed to use
               * to those supported by the microphone.
               */
              .min_pdm_clk_freq = 1280000,
              .max_pdm_clk_freq = 1280000,
              .min_pdm_clk_dc = 45,
              .max_pdm_clk_dc = 55,
          },
      .streams = &stream,
      .channel =
          {
              .req_num_streams = 1,
          },
  };

Please let me know if you need more information, thank you.

Best regards,

Kevin

RE: How do I adjust the PDM clock frequency and PDMCLKCTRL register value of the nRF5340?

Håkon Alseth — Thu, 18 Dec 2025 14:16:58 GMT

Hi,

If you want to source the PDM from the PCLK32M, you can set this in the clock-source in your device tree entry, like this:

https://github.com/nrfconnect/sdk-zephyr/blob/ncs-v3.2.0/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.dts#L52

then you can limit the min/max frequency setin the your "cfg" variable (type struct dmic_cfg)

Kind regards,

Håkon