nRF5340 PDM CLK duty cycle

RE: nRF5340 PDM CLK duty cycle

Ressa — Mon, 05 Jan 2026 13:40:26 GMT

Hi Poki,

That's a good observation but there is no official document to guarantee that observation for all conditions. But as a general rule you would expect stable signal characteristics for lower frequencies as you observed.

RE: nRF5340 PDM CLK duty cycle

Poki Huang — Mon, 05 Jan 2026 11:22:28 GMT

Hi Ressa:

What about my question 2? We change the frequency and from 1.28MHz to 960KHz and find the duty cycle from 55.54% to 49.97%, we test two pcbs and the result is the same, so can we use this frequency setting to let the ducy cycle inside our DMIC spec.? Or the duty cycle may change if next time with different lot/date code of nRF5340?

Thank you

Poki

RE: nRF5340 PDM CLK duty cycle

Ressa — Mon, 05 Jan 2026 10:20:04 GMT

Hi Poki,

Duty cycle of clock signal for PDM cannot be controlled and the variation mentioned in "PDM Electrical Specification" is due to internal hardware specs.

Best regards,
Ressa