<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/126808/nrf54l15-design-verification</link><description>I really need to verify this design for nrf54L15 SoC. If someone can go through it and confirm if it is okay or I need to make any changes ? I had made nRF52832 board but it did not work. So I want this design to be thoroughly verified, especially the</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Thu, 26 Mar 2026 06:33:08 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/126808/nrf54l15-design-verification" /><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/564068?ContentTypeID=1</link><pubDate>Thu, 26 Mar 2026 06:33:08 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ac8952a5-1b87-4eab-abe4-5006a5871d61</guid><dc:creator>PoojaK</dc:creator><description>&lt;p&gt;Okay. Thank&amp;nbsp; you. I will do s&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/564027?ContentTypeID=1</link><pubDate>Wed, 25 Mar 2026 11:36:38 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:89a0ba8d-7a99-4b4d-8b93-9aaacadb5389</guid><dc:creator>Szabolcs</dc:creator><description>&lt;p&gt;I see, so that the issue is with the wireless part of the software. What exactly are you experiencing, do you not see any RF output from the PCB?&lt;/p&gt;
&lt;p&gt;It is very unlikely that the problem is with the hardware. Your gerber files look fine, and even if the matching network&amp;nbsp;was completely wrong, you should see some signs of wireless activity (e.g. phone picking up BLE Advertising within a meter, spectrum analyzer showing a weak signal, etc.). So I do believe that this is a firmware issue which can be solved.&lt;/p&gt;
&lt;p&gt;Unfortunately, it is not possible to use 0603 components in the RF section, as these have completely different characteristics than the 0201 components. The matching network is very sensitive to the layout and component values due to the high frequencies.&lt;/p&gt;
&lt;p&gt;Please open another ticket where you describe how you created your firmware project, what example you used and what modifications you made. One of my coworkers specialized in firmware development will support you with debugging your project.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/563995?ContentTypeID=1</link><pubDate>Wed, 25 Mar 2026 07:58:20 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:9e6f5558-dfb2-4b9a-9dc5-8866acc5f926</guid><dc:creator>PoojaK</dc:creator><description>&lt;p&gt;The program is getting dumped correctly in the custom PCB. The issue is with the RF section. None of the wireless protocols are working. There is some major issue with the antenna section and impedance matching section. I will share the gerber and final design files. Also please can you verify if the components in antenna section are correctly tracked, and if we can use components of 0603 package and place them at a reasonable distance from each other. I was very disappointed that even after taking care in the placement and routing, the RF part is not working.&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/8322.GERBER_2D00_SPJ_5F00_NORDIC_5F00_NRF_2D00_V1.zip"&gt;devzone.nordicsemi.com/.../8322.GERBER_2D00_SPJ_5F00_NORDIC_5F00_NRF_2D00_V1.zip&lt;/a&gt;&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/0841.NORDIC_2D00_NRF_2D00_V1.sch"&gt;devzone.nordicsemi.com/.../0841.NORDIC_2D00_NRF_2D00_V1.sch&lt;/a&gt;&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/2068.NORDIC_2D00_NRF_2D00_V1.brd"&gt;devzone.nordicsemi.com/.../2068.NORDIC_2D00_NRF_2D00_V1.brd&lt;/a&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/563931?ContentTypeID=1</link><pubDate>Tue, 24 Mar 2026 09:30:07 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:6d6dedd3-8b54-41de-8d11-1e1ebce56b29</guid><dc:creator>Szabolcs</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;Please see&amp;nbsp;&lt;a href="https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/create_application.html"&gt;Creating an application&lt;/a&gt;&amp;nbsp;in the Nordic documentation page, and also the Developing with custom boards section. Your target SoC is nrf54l15.&lt;/p&gt;
&lt;p&gt;If you open the nRF Connect extension in VS Code, you&amp;#39;ll see the option &amp;quot;Flash&amp;quot;. You&amp;#39;ll need to have a debugger connected to the SWD pins on your board, this could be a SEGGER J-Link, a Nordic DevKit, etc.&lt;/p&gt;
&lt;p&gt;Is there a specific step you are stuck on?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/563862?ContentTypeID=1</link><pubDate>Mon, 23 Mar 2026 12:35:54 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:2c4e8f67-9ad4-4f3b-bc16-8e9966d22a51</guid><dc:creator>PoojaK</dc:creator><description>&lt;p&gt;I have got the PCB assembled now. How do i flash the program in it using VS Code and which SoC i should select&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/561084?ContentTypeID=1</link><pubDate>Fri, 13 Feb 2026 09:10:26 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:c3a7ded0-1926-453c-ace7-7b9863b9096b</guid><dc:creator>Szabolcs</dc:creator><description>&lt;p&gt;Any generic substrate will do fine. Our recommendation is to have a prepreg thickness less than 100um (between top and first inner layer).&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/561063?ContentTypeID=1</link><pubDate>Fri, 13 Feb 2026 01:50:57 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:68b8631a-cd9f-494a-affb-cdbaff2108e4</guid><dc:creator>PoojaK</dc:creator><description>&lt;p&gt;Thank you so much. I will give this PCB for manufacturing. Is there any specific substrate that I should use ? I will also start to look into firmware side now.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/561005?ContentTypeID=1</link><pubDate>Thu, 12 Feb 2026 12:34:32 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:10ce6af7-de66-4262-a8ef-d15ce288f28b</guid><dc:creator>Szabolcs</dc:creator><description>&lt;p&gt;I checked the design, everything looks OK now.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/560996?ContentTypeID=1</link><pubDate>Thu, 12 Feb 2026 11:45:12 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:20b6674a-4bad-49dd-9dbb-33eafcfef81d</guid><dc:creator>PoojaK</dc:creator><description>&lt;p&gt;I have updated the design as per your suggestion. Can you please take a look into it and suggest changes or corrections if any. Especially the triangle part mentioned above&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/4118.GERBER_2D00_SPJ_5F00_NORDIC_5F00_NRF_2D00_V1.zip"&gt;devzone.nordicsemi.com/.../4118.GERBER_2D00_SPJ_5F00_NORDIC_5F00_NRF_2D00_V1.zip&lt;/a&gt;&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/0880.NORDIC_2D00_NRF_2D00_V1.pdf"&gt;devzone.nordicsemi.com/.../0880.NORDIC_2D00_NRF_2D00_V1.pdf&lt;/a&gt;&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/2055.NORDIC_2D00_NRF_2D00_V1.brd"&gt;devzone.nordicsemi.com/.../2055.NORDIC_2D00_NRF_2D00_V1.brd&lt;/a&gt;&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/6746.NORDIC_2D00_NRF_2D00_V1.sch"&gt;devzone.nordicsemi.com/.../6746.NORDIC_2D00_NRF_2D00_V1.sch&lt;/a&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/560980?ContentTypeID=1</link><pubDate>Thu, 12 Feb 2026 09:04:07 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:3d9ef775-05ad-48ab-95b5-a942d5d62f72</guid><dc:creator>Szabolcs</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;R4 needs to be 1K.&lt;/p&gt;
&lt;p&gt;The other component values are all correct.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/560965?ContentTypeID=1</link><pubDate>Thu, 12 Feb 2026 04:49:19 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:71d308d0-c80c-4e54-8f04-698ee32b153b</guid><dc:creator>PoojaK</dc:creator><description>&lt;p&gt;Thank you for your prompt reply. I will make this change and upload the design. Anything else that I need to change in the schematic, component values, placement or routing. I am attaching the final schematic PDF here.&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/NORDIC_2D00_NRF_2D00_V1.pdf"&gt;devzone.nordicsemi.com/.../NORDIC_2D00_NRF_2D00_V1.pdf&lt;/a&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/560922?ContentTypeID=1</link><pubDate>Wed, 11 Feb 2026 13:47:56 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:5b9bdbeb-72cd-4dd7-9b5f-ac594fedc3a5</guid><dc:creator>Szabolcs</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;This looks better.&lt;/p&gt;
&lt;p&gt;On the C18 ground pin, place a filled triangle region on the vias and the pad, like in the picture:&lt;br /&gt;&lt;img style="max-height:240px;max-width:320px;" src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/pastedimage1770817572284v1.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;With these thin traces, you are introducing parasitic inductances between the vias, which is not good.&lt;/p&gt;
&lt;p&gt;You can also keep the ground in the inner layers below the matching, a closer ground plane reduces the harmonic emissions. Just place a cutout around the triangle of the 3 vias.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/560828?ContentTypeID=1</link><pubDate>Tue, 10 Feb 2026 16:08:37 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:c0719155-5ccc-4656-83f1-e490ee6430f8</guid><dc:creator>PoojaK</dc:creator><description>&lt;p&gt;Thank you so much. It gave me a very good insight. I have updated the design as per your suggestions. Please can you re-verify if it is okay now.&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/GERBER_2D00_SPJ_5F00_NORDIC_5F00_NRF_2D00_V1-_2800_1_2900_.zip"&gt;devzone.nordicsemi.com/.../GERBER_2D00_SPJ_5F00_NORDIC_5F00_NRF_2D00_V1-_2800_1_2900_.zip&lt;/a&gt;&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/NORDIC_2D00_NRF_2D00_V1.sch"&gt;devzone.nordicsemi.com/.../NORDIC_2D00_NRF_2D00_V1.sch&lt;/a&gt;&lt;a href="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/NORDIC_2D00_NRF_2D00_V1.brd"&gt;devzone.nordicsemi.com/.../NORDIC_2D00_NRF_2D00_V1.brd&lt;/a&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/560625?ContentTypeID=1</link><pubDate>Mon, 09 Feb 2026 10:10:27 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:c6fc0708-fe54-4de3-8cd9-14c045cef0c6</guid><dc:creator>Szabolcs</dc:creator><description>&lt;p&gt;Hi, I have edited my reply and added the explanations in &lt;em&gt;italics&lt;/em&gt;. I hope this clarifies things, let me know if I need to elaborate more.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/560593?ContentTypeID=1</link><pubDate>Sun, 08 Feb 2026 10:20:27 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:81ed00dd-a2cc-4e15-8307-b507ac29366b</guid><dc:creator>PoojaK</dc:creator><description>&lt;p&gt;Thank you so much for the response. Can you please explain why are these changes so critical for our design? Also I will make these changes and upload the files soon.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF54L15 Design Verification</title><link>https://devzone.nordicsemi.com/thread/560261?ContentTypeID=1</link><pubDate>Tue, 03 Feb 2026 16:58:17 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:cfc7c1d4-53d5-43aa-bbdf-9414944af249</guid><dc:creator>Szabolcs</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;I have reviewed your design, here is my feedback:&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;L1 should be 2.7nH. &lt;em&gt;The matching needs to be exactly the same as the reference design.&lt;/em&gt;&lt;/li&gt;
&lt;li&gt;Note: The exact value of C6 is known after antenna tuning. (It might not be needed.).&lt;/li&gt;
&lt;li&gt;C7 and C26 needs better grounding. &lt;em&gt;These long traces to ground add too much impedance.&lt;/em&gt;&lt;/li&gt;
&lt;li&gt;Do not connect C18 ground to the top polygon, only connect it on the bottom layer.&lt;em&gt; The matching network need this type of connection to suppress harmonic emissions correctly.&lt;/em&gt;&lt;br /&gt;&lt;img style="max-height:240px;max-width:320px;" src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/7506.pastedimage1770137101937v1.png" alt=" " /&gt;&lt;/li&gt;
&lt;li&gt;The ground keepout on the inner layers are not actually needed, and the performance is better without them.&lt;em&gt; The ground being closer to the matching shields harmonic emissions better.&lt;/em&gt;&lt;/li&gt;
&lt;li&gt;Ground plane should be extended further so it flows around the crystal up to the antenna. (Move the circuit to the left.) &lt;em&gt;The antenna needs a continuous ground layer to work correctly.&lt;/em&gt;&lt;br /&gt;&lt;img style="max-height:240px;max-width:320px;" src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/6011.pastedimage1770137858573v5.png" alt=" " /&gt;&lt;/li&gt;
&lt;li&gt;Connect the VDD trace like this: &lt;em&gt;(It is not critical, but better because of lower impedance between VDD pins.)&lt;/em&gt;&lt;br /&gt;&lt;img style="max-height:240px;max-width:320px;" src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/8176.pastedimage1770137505012v3.png" alt=" " /&gt;&lt;/li&gt;
&lt;li&gt;Push the DECA trace outwards so ground pour can flow between it and VDD. &lt;em&gt;This creates better shielding between VDD and DECA.&lt;/em&gt;&lt;br /&gt;&lt;img style="max-height:240px;max-width:320px;" src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/6758.pastedimage1770137594884v4.png" alt=" " /&gt;&lt;/li&gt;
&lt;li&gt;The right edge of the bottom GND pour is not vertical. &lt;em&gt;(Not critical, purely aesthetic.)&lt;/em&gt;&lt;/li&gt;
&lt;/ol&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>