Floating GPIO configuration

RE: Floating GPIO configuration

Szabolcs — Thu, 12 Feb 2026 15:28:42 GMT

Hugh, thank you for your insights.

Your measurements are consistent with the datasheet values, if we assume the pull-up/down resistors are 15K (11-16 by spec), then on all pins it yields a current of 3V/15K*32=6.4mA, just like you showed.

The pulling resistors being connected directly to the pin makes sense to me. For example. if you want an open-drain output, you would enable the pull-up resistor while disconnecting the input buffer. I agree that this is actually a mistake in the datasheet, the block diagram should show the connection of the pulling resistors, and the PIN[0].CNF.PULL register should be tied to them, not to the input buffer.

RE: Floating GPIO configuration

hmolesworth — Wed, 11 Feb 2026 18:13:10 GMT

I agree with your comments on the drawing, however it is not strictly accurate in the case of the nRF52 series - I haven't checked the nRF54 yet. I say this as the input pullup/pulldown is shown downwind of the input disconnect but even when the disconnect (nRF52) is open the pullup/pulldown still affects the pin; I have tested this. If the pullup/pulldown is always connected to the pin, then an input FET hi/lo might also always be connected prior to the input disconnect circuit.

Here are some older results on the nRF52832, with input disconnect and nothing connected to all 32 io pins the current increases to 6.47mA when driving low with pullup enabled and similar when driving high with pulldown enabled.

All 32 io pins have no external connections; all 32 pins driven identically

 PPK     Measured
 ======  ========
 1.66uA  2.971V with errata workarounds, no i/o
 1.51uA  2.985V no errata workarounds, no i/o
 1.49uA  2.989V (PIN_OUTPUT | DISCONNECT | PULLNONE | FORCE_S0S1 | SENSE_OFF) Drive Low
 1.49uA  2.999V (PIN_OUTPUT | DISCONNECT | PULLDOWN | FORCE_S0S1 | SENSE_OFF) Drive Low
 6.47mA  2.894V (PIN_OUTPUT | DISCONNECT | PULLUP   | FORCE_S0S1 | SENSE_OFF) Drive Low
 6.47mA  2.889V (PIN_OUTPUT | CONNECT    | PULLUP   | FORCE_S0S1 | SENSE_OFF) Drive Low

 1.51uA  2.959V (PIN_OUTPUT | DISCONNECT | PULLNONE | FORCE_S0S1 | SENSE_OFF) Drive High
 6.42mA  2.877V (PIN_OUTPUT | DISCONNECT | PULLDOWN | FORCE_S0S1 | SENSE_OFF) Drive High
 1.53uA  2.938V (PIN_OUTPUT | DISCONNECT | PULLUP   | FORCE_S0S1 | SENSE_OFF) Drive High
 6.47uA  2.889V (PIN_OUTPUT | CONNECT    | PULLUP   | FORCE_S0S1 | SENSE_OFF) Drive High

The nRF54 may behave differently, but the datasheet schematic looks similar so my suggestion is to test this. The pullup/pulldown circuit sitting prior to the input disconnect may be irrelevant here, but I would still test for feedthrough by slow ramping input voltages to io pins to be sure; the more pins tested simultaneously the bigger the feedthrough (if any, hopefully none). Of course if oodles of power are available then feedthrough may not really be an issue and can be ignored.

RE: Floating GPIO configuration

Szabolcs — Wed, 11 Feb 2026 12:28:56 GMT

You can see the GPIO block diagram in the nRF54LM20A datasheet:

Here, you can see that there is a switch before the input buffer stage, hence the name "Input buffer disconnect". In this mode, the buffer stage is actually isolated from the GPIO pin. So in this mode, the issue you mentioned is not relevant.

Unfortunately, we don't have more detailed information on these switches, but they can be assumed to be "almost-ideal" analog switches.

If you need to have a pin with very specific characteristic, you could use a tri-state buffer or line driver (for example something from the 74xx series).

RE: Floating GPIO configuration

hmolesworth — Tue, 10 Feb 2026 19:58:15 GMT

"Input buffer disconnect" mode may well do what you require, but I would argue that it would be better to test this on the specific nRF as there is no clear description of where the disconnect is internally physically placed. There is a vanishingly small window somewhere near VDD/2 where slow or floating input feedthrough leakage may occur; this is not leakage into or out of the io pin but instead leakage through internal FETs from internal VDD to internal GND caused by high and low FETs being slightly biased on by an input voltage falling within that window. If input disconnect mode isolates all such FETs then maybe there is no issue, but I don't see this guaranteed.

More info here; all semi manufacturers discuss this, this is TI: scba004e.pdf

RE: Floating GPIO configuration

Szabolcs — Tue, 10 Feb 2026 15:35:21 GMT

Hi Adam,

If you configure the GPIO in "Input buffer disconnect" mode, with pull-up/down disabled, you can assume the input impedance to be at least 100 MOhm, with a capacitance of less than 5 pF, not including the pad/trace parasitics. The datasheet does not include these numbers, because they are very high and hard to measure accurately.