Next buffers not supplied on time

RE: Next buffers not supplied on time

Maria Gilje — Thu, 05 Mar 2026 12:39:30 GMT

Hi,

I noticed that you created yet another ticket about this issue which my colleague picked up. Please avoid creating multiple tickets on the same issue.

I will be away next week, so I will close this ticket since you have another open ticket on this issue.

Best regards,

Maria

RE: Next buffers not supplied on time

Sharon123 — Wed, 25 Feb 2026 07:04:37 GMT

Maria Gilje

RE: Next buffers not supplied on time

Sharon123 — Tue, 24 Feb 2026 02:29:12 GMT

ok mam.

I am actually stuck in here

Thanks you for your feed back'

I hope you should find the replay as soon as possible

RE: Next buffers not supplied on time

Maria Gilje — Mon, 23 Feb 2026 15:15:06 GMT

Hello,

I was not able to find further feedback for you today. My apologies for the delay.

Best regards,

Maria

RE: Next buffers not supplied on time

Sharon123 — Fri, 20 Feb 2026 11:37:05 GMT

During this transmission time also no sound is generated

RE: Next buffers not supplied on time

Sharon123 — Fri, 20 Feb 2026 11:36:23 GMT

*** Booting nRF Connect SDK v3.2.1-d8887f6f32df ***
*** Using Zephyr OS v4.2.99-ec78104f1569 ***
I2S playback (mem_slab)
PWM configured: period=250ns pulse=125ns
I2C bus ready, addr=0x18
Codec responded: reg0 = 0x01
Writing codec register table...
reg=0x01 val=0x01 err=0
reg=0x04 val=0x03 err=0
reg=0x05 val=0xD4 err=0
reg=0x06 val=0x20 err=0
reg=0x07 val=0x00 err=0
reg=0x08 val=0x00 err=0
reg=0x1B val=0x0C err=0
reg=0x0B val=0x84 err=0
reg=0x0C val=0x99 err=0
reg=0x0E val=0x80 err=0
reg=0x1D val=0x01 err=0
reg=0x1E val=0x84 err=0
reg=0x3C val=0x00 err=0
reg=0x3D val=0x00 err=0
reg=0x3F val=0xD6 err=0
reg=0x40 val=0x00 err=0
reg=0x41 val=0x00 err=0
reg=0x42 val=0x00 err=0
reg=0x1E val=0x00 err=0
reg=0x1F val=0xC0 err=0
reg=0x20 val=0xC6 err=0
reg=0x23 val=0xA8 err=0
reg=0x24 val=0x80 err=0
reg=0x25 val=0x80 err=0
reg=0x22 val=0x30 err=0
reg=0x2A val=0x3D err=0
reg=0x2B val=0x3D err=0
reg=0x2C val=0xC0 err=0
reg=0x26 val=0x80 err=0
reg=0x27 val=0x80 err=0
reg=0x2E val=0x00 err=0
reg=0x2F val=0x00 err=0
reg=0x30 val=0x00 err=0
reg=0x31 val=0x00 err=0
Codec init DONE.
I2C ready
Start streaming
[00:04:02.658,525] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200070d8
[00:04:02.658,775] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200075d8
[00:04:02.659,020] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20007ad8
[00:04:02.659,262] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20007fd8
[00:04:02.659,507] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200084d8
[00:04:02.659,751] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200089d8
[00:04:02.659,996] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20008ed8
[00:04:02.660,240] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200093d8
[00:04:02.660,484] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200098d8
[00:04:02.660,729] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20009dd8
[00:04:02.660,973] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000a2d8
[00:04:02.661,217] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000a7d8
[00:04:02.661,461] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000acd8
[00:04:02.661,702] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000b1d8
[00:04:02.661,943] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000b6d8
[00:04:02.662,184] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000bbd8
[00:04:02.662,425] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000c0d8
[00:04:02.662,666] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000c5d8
[00:04:02.667,909] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000cad8
[00:04:02.668,153] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000cfd8
[00:04:02.668,398] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000d4d8
[00:04:02.668,642] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000d9d8
[00:04:02.668,886] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000ded8
[00:04:02.669,131] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000e3d8
[00:04:02.669,375] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000e8d8
[00:04:02.669,618] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000edd8
[00:04:02.669,859] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000f2d8
[00:04:02.670,100] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000f7d8
[00:04:02.670,340] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x2000fcd8
[00:04:02.670,581] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200101d8
[00:04:02.670,853] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200106d8
[00:04:02.671,107] <dbg> i2s_nrfx: [00:04:02.671,260] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200075d8/(nil)
i2s_nrfx_write: Queued TX 0x20010bd8
[00:04:02.671,623] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200110d8
[00:04:02.676,870] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200115d8
[00:04:02.709,809] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200070d8
[00:04:02.710,047] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20007ad8/(nil)
[00:04:02.710,285] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20011ad8
[00:04:02.748,371] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200075d8
[00:04:02.748,608] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20007fd8/(nil)
[00:04:02.748,849] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20011d58
[00:04:02.786,924] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20007ad8
[00:04:02.787,161] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200084d8/(nil)
[00:04:02.787,402] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20011fd8
[00:04:02.825,457] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20007fd8
[00:04:02.825,695] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200089d8/(nil)
[00:04:02.825,935] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20012258
[00:04:02.864,014] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200084d8
[00:04:02.864,250] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20008ed8/(nil)
[00:04:02.864,490] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200124d8
[00:04:02.902,563] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200089d8
[00:04:02.902,800] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200093d8/(nil)
[00:04:02.903,041] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20012758
[00:04:02.941,131] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20008ed8
[00:04:02.941,368] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200098d8/(nil)
[00:04:02.941,609] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200129d8
[00:04:02.979,687] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200093d8
[00:04:02.979,925] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20009dd8/(nil)
[00:04:02.980,165] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20012c58
[00:04:03.018,230] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200098d8
[00:04:03.018,466] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000a2d8/(nil)
[00:04:03.018,704] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20012ed8
[00:04:03.056,802] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20009dd8
[00:04:03.057,038] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000a7d8/(nil)
[00:04:03.057,276] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20013158
[00:04:03.095,357] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000a2d8
[00:04:03.095,593] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000acd8/(nil)
[00:04:03.095,832] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200133d8
[00:04:03.133,902] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000a7d8
[00:04:03.134,140] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000b1d8/(nil)
[00:04:03.134,380] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20013658
[00:04:03.172,445] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000acd8
[00:04:03.172,682] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000b6d8/(nil)
[00:04:03.172,921] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200138d8
[00:04:03.211,010] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000b1d8
[00:04:03.211,246] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000bbd8/(nil)
[00:04:03.211,486] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20013b58
[00:04:03.249,578] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000b6d8
[00:04:03.249,815] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000c0d8/(nil)
[00:04:03.250,056] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20013dd8
[00:04:03.288,126] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000bbd8
[00:04:03.288,364] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000c5d8/(nil)
[00:04:03.288,604] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20014058
[00:04:03.326,686] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000c0d8
[00:04:03.326,924] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000cad8/(nil)
[00:04:03.327,162] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200142d8
[00:04:03.365,230] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000c5d8
[00:04:03.365,468] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000cfd8/(nil)
[00:04:03.365,708] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20014558
[00:04:03.403,790] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000cad8
[00:04:03.404,027] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000d4d8/(nil)
[00:04:03.404,266] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200147d8
[00:04:03.442,371] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000cfd8
[00:04:03.442,608] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000d9d8/(nil)
[00:04:03.442,849] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20014a58
[00:04:03.480,943] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000d4d8
[00:04:03.481,180] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000ded8/(nil)
[00:04:03.481,419] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20014cd8
[00:04:03.519,494] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000d9d8
[00:04:03.519,732] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000e3d8/(nil)
[00:04:03.519,972] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20014f58
[00:04:03.558,068] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000ded8
[00:04:03.558,304] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000e8d8/(nil)
[00:04:03.558,545] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200151d8
[00:04:03.596,598] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000e3d8
[00:04:03.596,836] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000edd8/(nil)
[00:04:03.597,077] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20015458
[00:04:03.635,159] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000e8d8
[00:04:03.635,396] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000f2d8/(nil)
[00:04:03.635,634] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200156d8
[00:04:03.673,719] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000edd8
[00:04:03.673,957] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000f7d8/(nil)
[00:04:03.674,197] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20015958
[00:04:03.712,268] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000f2d8
[00:04:03.712,505] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x2000fcd8/(nil)
[00:04:03.712,746] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20015bd8
[00:04:03.750,833] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000f7d8
[00:04:03.751,071] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200101d8/(nil)
[00:04:03.751,310] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20015e58
[00:04:03.789,400] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x2000fcd8
[00:04:03.789,638] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200106d8/(nil)
[00:04:03.789,876] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200160d8
[00:04:03.827,970] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200101d8
[00:04:03.828,208] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20010bd8/(nil)
[00:04:03.828,448] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20016358
[00:04:03.866,527] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200106d8
[00:04:03.866,765] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200110d8/(nil)
[00:04:03.867,005] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200165d8
[00:04:03.905,088] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20010bd8
[00:04:03.905,324] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200115d8/(nil)
[00:04:03.905,565] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20016858
[00:04:03.943,635] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200110d8
[00:04:03.943,872] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20011ad8/(nil)
[00:04:03.944,111] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20016ad8
[00:04:03.982,205] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200115d8
[00:04:03.982,443] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20011d58/(nil)
[00:04:03.982,683] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20016d58
[00:04:04.020,775] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20011ad8
[00:04:04.021,011] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20011fd8/(nil)
[00:04:04.021,248] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20016fd8
[00:04:04.059,333] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20011d58
[00:04:04.059,569] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20012258/(nil)
[00:04:04.059,808] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20017258
[00:04:04.097,885] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20011fd8
[00:04:04.098,121] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200124d8/(nil)
[00:04:04.098,357] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200174d8
[00:04:04.136,452] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20012258
[00:04:04.136,690] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20012758/(nil)
[00:04:04.136,930] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20017758
[00:04:04.175,015] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200124d8
[00:04:04.175,251] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200129d8/(nil)
[00:04:04.175,491] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200179d8
[00:04:04.213,583] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20012758
[00:04:04.213,821] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20012c58/(nil)
[00:04:04.214,061] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20017c58
[00:04:04.252,153] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200129d8
[00:04:04.252,390] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20012ed8/(nil)
[00:04:04.252,629] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20017ed8
[00:04:04.290,698] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20012c58
[00:04:04.290,936] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20013158/(nil)
[00:04:04.291,176] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20018158
[00:04:04.329,235] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20012ed8
[00:04:04.329,472] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200133d8/(nil)
[00:04:04.329,713] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200183d8
[00:04:04.367,778] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20013158
[00:04:04.368,016] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20013658/(nil)
[00:04:04.368,255] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20018658
[00:04:04.406,335] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200133d8
[00:04:04.406,573] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200138d8/(nil)
[00:04:04.406,810] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200188d8
[00:04:04.444,879] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20013658
[00:04:04.445,117] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20013b58/(nil)
[00:04:04.445,357] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20018b58
[00:04:04.483,440] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200138d8
[00:04:04.483,678] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20013dd8/(nil)
[00:04:04.483,918] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20018dd8
[00:04:04.522,019] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20013b58
[00:04:04.522,255] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20014058/(nil)
[00:04:04.522,496] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20019058
[00:04:04.560,566] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20013dd8
[00:04:04.560,803] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200142d8/(nil)
[00:04:04.561,041] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200192d8
[00:04:04.599,132] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20014058
[00:04:04.599,370] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20014558/(nil)
[00:04:04.599,610] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20019558
[00:04:04.637,698] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200142d8
[00:04:04.637,936] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200147d8/(nil)
[00:04:04.638,176] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x200197d8
[00:04:04.676,266] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20014558
[00:04:04.676,486] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20014a58/(nil)
[00:04:04.676,735] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20014558
[00:04:04.714,832] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200147d8
[00:04:04.715,051] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20014cd8/(nil)
[00:04:04.753,394] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20014a58
[00:04:04.753,614] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20014f58/(nil)
[00:04:04.753,863] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20014a58
[00:04:04.791,948] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20014cd8
[00:04:04.792,167] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200151d8/(nil)
[00:04:04.830,527] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20014f58
[00:04:04.830,747] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20015458/(nil)
[00:04:04.830,996] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20014f58
[00:04:04.869,096] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200151d8
[00:04:04.869,313] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200156d8/(nil)
[00:04:04.907,632] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20015458
[00:04:04.907,851] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20015958/(nil)
[00:04:04.908,097] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20015458
[00:04:04.946,197] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200156d8
[00:04:04.946,415] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20015bd8/(nil)
[00:04:04.984,770] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20015958
[00:04:04.984,990] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20015e58/(nil)
[00:04:04.985,239] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20015958
[00:04:05.023,316] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20015bd8
[00:04:05.023,533] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200160d8/(nil)
[00:04:05.061,887] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20015e58
[00:04:05.062,105] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20016358/(nil)
[00:04:05.062,353] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20015e58
[00:04:05.100,432] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200160d8
[00:04:05.100,650] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200165d8/(nil)
[00:04:05.138,977] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20016358
[00:04:05.139,197] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20016858/(nil)
[00:04:05.139,446] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20016358
[00:04:05.177,542] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200165d8
[00:04:05.177,760] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20016ad8/(nil)
[00:04:05.216,098] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20016858
[00:04:05.216,316] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20016d58/(nil)
[00:04:05.216,565] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20016858
[00:04:05.254,647] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20016ad8
[00:04:05.254,865] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20016fd8/(nil)
[00:04:05.293,199] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20016d58
[00:04:05.293,419] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20017258/(nil)
[00:04:05.293,668] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20016d58
[00:04:05.331,752] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20016fd8
[00:04:05.331,971] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200174d8/(nil)
[00:04:05.370,317] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20017258
[00:04:05.370,536] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20017758/(nil)
[00:04:05.370,786] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20017258
[00:04:05.408,874] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200174d8
[00:04:05.409,093] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200179d8/(nil)
[00:04:05.447,435] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20017758
[00:04:05.447,654] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20017c58/(nil)
[00:04:05.447,901] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20017758
[00:04:05.485,992] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200179d8
[00:04:05.486,211] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20017ed8/(nil)
[00:04:05.524,539] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20017c58
[00:04:05.524,759] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20018158/(nil)
[00:04:05.525,008] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20017c58
[00:04:05.563,086] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20017ed8
[00:04:05.563,303] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200183d8/(nil)
[00:04:05.601,649] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20018158
[00:04:05.601,868] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20018658/(nil)
[00:04:05.602,118] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20018158
[00:04:05.640,204] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200183d8
[00:04:05.640,420] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200188d8/(nil)
[00:04:05.678,771] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20018658
[00:04:05.678,991] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20018b58/(nil)
[00:04:05.679,240] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20018658
[00:04:05.717,322] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200188d8
[00:04:05.717,540] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20018dd8/(nil)
[00:04:05.755,891] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20018b58
[00:04:05.756,110] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20019058/(nil)
[00:04:05.756,360] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20018b58
[00:04:05.794,457] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20018dd8
[00:04:05.794,676] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200192d8/(nil)
[00:04:05.833,007] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20019058
[00:04:05.833,224] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20019558/(nil)
[00:04:05.833,473] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20019058
[00:04:05.871,568] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200192d8
[00:04:05.871,786] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x200197d8/(nil)
[00:04:05.910,127] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20019558
[00:04:05.910,346] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20014558/(nil)
[00:04:05.910,596] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20019558
[00:04:05.948,688] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x200197d8
[00:04:05.948,907] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20014a58/(nil)
[00:04:05.987,245] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20014558
[00:04:05.987,465] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20014f58/(nil)
[00:04:05.987,713] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20014558
[00:04:06.025,811] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20014a58
[00:04:06.026,028] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20015458/(nil)
[00:04:06.064,392] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20014f58
[00:04:06.064,610] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20015958/(nil)
[00:04:06.064,858] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20014f58
[00:04:06.102,965] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20015458
[00:04:06.103,183] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20015e58/(nil)
[00:04:06.141,520] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20015958
[00:04:06.141,739] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20016358/(nil)
[00:04:06.141,989] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20015958
[00:04:06.180,082] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20015e58
[00:04:06.180,298] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20016858/(nil)
[00:04:06.218,658] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20016358
[00:04:06.218,878] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20016d58/(nil)
[00:04:06.219,127] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20016358
[00:04:06.257,229] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20016858
[00:04:06.257,447] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20017258/(nil)
[00:04:06.295,797] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20016d58
[00:04:06.296,017] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20017758/(nil)
[00:04:06.296,265] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20016d58
[00:04:06.334,347] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20017258
[00:04:06.334,565] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20017c58/(nil)
[00:04:06.372,898] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20017758
[00:04:06.373,116] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20018158/(nil)
[00:04:06.373,362] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20017758
[00:04:06.411,476] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20017c58
[00:04:06.411,695] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20018658/(nil)
[00:04:06.450,044] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20018158
[00:04:06.450,262] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20018b58/(nil)
[00:04:06.450,511] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20018158
[00:04:06.488,589] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20018658
[00:04:06.488,808] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20019058/(nil)
[00:04:06.527,147] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20018b58
[00:04:06.527,366] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20019558/(nil)
[00:04:06.527,616] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20018b58
[00:04:06.565,705] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20019058
[00:04:06.565,924] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20014558/(nil)
[00:04:06.604,295] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20019558
[00:04:06.604,515] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20014f58/(nil)
[00:04:06.604,765] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20019558
[00:04:06.642,852] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20014558
[00:04:06.643,071] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20015958/(nil)
[00:04:06.681,413] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20014f58
[00:04:06.681,633] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20016358/(nil)
[00:04:06.681,882] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20014f58
[00:04:06.719,971] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20015958
[00:04:06.720,190] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20016d58/(nil)
[00:04:06.758,531] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20016358
[00:04:06.758,751] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20017758/(nil)
[00:04:06.759,000] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20016358
[00:04:06.797,119] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20016d58
[00:04:06.797,337] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20018158/(nil)
[00:04:06.835,696] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20017758
[00:04:06.835,916] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20018b58/(nil)
[00:04:06.836,165] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20017758
[00:04:06.874,263] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20018158
[00:04:06.874,482] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20019558/(nil)
[00:04:06.912,836] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20018b58
[00:04:06.913,055] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20014f58/(nil)
[00:04:06.913,300] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20018b58
[00:04:06.951,422] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20019558
[00:04:06.951,640] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20016358/(nil)
[00:04:06.989,991] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20014f58
[00:04:06.990,211] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20017758/(nil)
[00:04:06.990,460] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20014f58
[00:04:07.028,551] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20016358
[00:04:07.028,768] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20018b58/(nil)
[00:04:07.067,107] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20017758
[00:04:07.067,325] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20014f58/(nil)
[00:04:07.067,573] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20017758
[00:04:07.105,674] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20018b58
[00:04:07.105,892] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20017758/(nil)
[00:04:07.144,230] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20014f58
[00:04:07.144,464] <dbg> i2s_nrfx: i2s_nrfx_write: Queued TX 0x20014f58
[00:04:07.144,675] <dbg> i2s_nrfx: i2s_nrfx_write: Next TX 0x20014f58
[00:04:07.144,881] <dbg> i2s_nrfx: supply_next_buffers: Next buffers: 0x20014f58/(nil)
[00:04:07.182,796] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20017758
[00:04:07.221,344] <err> i2s_nrfx: Next buffers not supplied on time
[00:04:07.221,560] <dbg> i2s_nrfx: free_tx_buffer: Freed TX 0x20014f58
[00:04:07.221,803] <err> i2s_nrfx: Cannot write in state: 4
I2S error -5
ASSERTION FAIL [p_cb->state != NRFX_DRV_STATE_UNINITIALIZED] @ WEST_TOPDIR/modules/hal/nordic/nrfx/drivers/src/nrfx_i2s.c:439
[00:04:07.222,272] <err> os: r0/a1: 0x00000004 r1/a2: 0x000001b7 r2/a3: 0x00000000
[00:04:07.222,507] <err> os: r3/a4: 0x00000004 r12/ip: 0x0000000a r14/lr: 0x00007f41
[00:04:07.222,734] <err> os: xpsr: 0x09000000
[00:04:07.222,907] <err> os: Faulting instruction address (r15/pc): 0x0000e38a
[00:04:07.223,118] <err> os: >>> ZEPHYR FATAL ERROR 4: Kernel panic on CPU 0
[00:04:07.223,330] <err> os: Current thread: 0x20000a28 (main)
[00:04:07.223,526] <err> os: Halting system

this is log when i am update - instance

RE: Next buffers not supplied on time

Sharon123 — Fri, 20 Feb 2026 10:14:15 GMT

Hi mam,

I am currently generating Sine sound using nrf as slave and codec has master -

so any issue have for this config.

i am connecting my nrf Sdout - to codec Sdin

Bclk ,mclk,wclk generated by codec now config as nrf -slave

I got mic sound from codec - But i did not get proper out -

Dout shows .5v only

RE: Next buffers not supplied on time

Sharon123 — Fri, 20 Feb 2026 10:00:18 GMT

ok Thank you

RE: Next buffers not supplied on time

Maria Gilje — Fri, 20 Feb 2026 09:55:30 GMT

Hello,

Thank you for sharing code with Insert->Code.

You have some instance collisions in your overlay, i.e. uart20, i2s20 and pwm20. Please choose unique instances for all your peripherals.

Best regards,

Maria

RE: Next buffers not supplied on time

Sharon123 — Thu, 19 Feb 2026 15:55:42 GMT

Hi Maria,

1. my i2s is slave and codec is master

2.I tried Thread creation and Working queue methord but same issue is face.

3.I2c is used for register write ans I2s is used for Tx .

4.i2c is initialization is done , I2s Tx happen some buffer after its goes to Buffer Error .

5. I tried different methird and Verify - MCLK,BCLK,LRCK is proper

6. when i check Din - it shows Millivolt range

I will share my Entire Code below For your Reference

/*
 * Codec-style I2S SLAVE playback using k_mem_slab
 * nRF54Lx DK
 */

#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/i2s.h>
#include <zephyr/sys/printk.h>
#include "codec/codec.h"

#define I2S_NODE DT_NODELABEL(i2s20)

//audio
#define SAMPLE_RATE_HZ     8000
#define SAMPLE_BIT_WIDTH   16
#define CHANNELS           2
#define SAMPLES_PER_BLOCK  160
//#define SAMPLES_PER_BLOCK  (SAMPLE_RATE_HZ / 10)    // 33ms blocks
#define BLOCK_SIZE         (SAMPLES_PER_BLOCK * CHANNELS * sizeof(int16_t))
#define NUM_BLOCKS         120
#define TIMEOUT_MS         2000

// #define AUDIO_THREAD_STACK 2048
// #define AUDIO_THREAD_PRIO  -2   

// K_THREAD_STACK_DEFINE(audio_stack, AUDIO_THREAD_STACK);
// static struct k_thread audio_thread;



// K_THREAD_STACK_DEFINE(i2s_stack, I2S_THREAD_STACK);
// static struct k_thread i2s_thread_data;

static const struct device *i2s_dev = DEVICE_DT_GET(I2S_NODE);

//  memory slab for I2S TX buffers
K_MEM_SLAB_DEFINE(i2s_tx_slab, BLOCK_SIZE, NUM_BLOCKS, 4);

//sine
// static int16_t sine_lut[] = {
//     3211, 6392, 9511, 12539, 15446, 18204, 20787, 23169,
//     25329, 27244, 28897, 30272, 31356, 32137, 32609, 32767,
//     -3212, -6393, -9512, -12540, -15447, -18205, -20788, -23170,
//     -25330, -27245, -28898, -30273, -31357, -32138, -32610, -32767};


static int16_t sine_lut[] = {
    6392,  12539,  18204,  23169,  27244,  30272,  32137,  32767,  32137,
    30272, 27244, 23169, 18204, 12539, 6392, 0, -6393, -12540,
    -18205, -23170, -27245, -30273, -32138, -32767, -32138, -30273, -27245,
    -23170, -18205, -12540, -6393, -1};

// static int16_t sine_lut[8] = {
//      0,
//  23170,
//  32767,
//  23170,
//      0,
// -23170,
// -32768,
// -23170
// };


// Fill block
static void fill_block(int16_t *buf)
{
    int lut_len = ARRAY_SIZE(sine_lut);

    for (int i = 0; i < SAMPLES_PER_BLOCK; i++)
    {
        int16_t s = sine_lut[i % lut_len];
        buf[2 * i] = s;
        buf[2 * i + 1] = s;
        // buf[i] = 28000;
    }
}

// // thread creation
// void audio_thread_fn(void *a, void *b, void *c)
// {
//     while (1)
//     {
//         void *block;
//         int ret;

//         ret = k_mem_slab_alloc(&i2s_tx_slab, &block, K_NO_WAIT);
//         if (ret != 0)
//         {
//             k_yield();   // allow DMA + ISR
//             continue;
//         }

//         fill_block((int16_t *)block);

//         ret = i2s_buf_write(i2s_dev, block, BLOCK_SIZE);

//         if (ret == -ENOMEM)
//         {
//             k_mem_slab_free(&i2s_tx_slab, block);
//         }
//         else if (ret < 0)
//         {
//             printk("I2S error %d\n", ret);
//             k_mem_slab_free(&i2s_tx_slab, block);
//         }
//     }
// }



int main(void)
{
    struct i2s_config cfg;
    int ret;

    printk("I2S playback (mem_slab)\n");

    // clocking and codec init
    ret = pwm_4mhz();
    if (ret < 0)
    {
        printk("PWM init failed\n");
        return ret;
    }

    for (int i = 0; i < 20; i++)
    {
        ret = i2c_init_codec();
        if (ret == 0)
        {
            break;
        }
        k_msleep(5);
    }
    if (ret < 0)
    {
        printk("Codec init failed\n");
        return ret;
    }

    k_msleep(10);
    // printk("BLOCK=%d  SAMPLES=%d\n", BLOCK_SIZE, SAMPLES_PER_BLOCK);

    if (!device_is_ready(i2s_dev))
    {
        printk("I2S not ready\n");
        return -ENODEV;
    }

    // I2S CONFIG
    cfg.word_size      = SAMPLE_BIT_WIDTH;
    cfg.channels       = CHANNELS;
    cfg.format         =I2S_FMT_DATA_FORMAT_I2S;;   //cfg.format = I2S_FMT_DATA_FORMAT_LEFT_JUSTIFIED;

    cfg.options        = I2S_OPT_FRAME_CLK_SLAVE |
                         I2S_OPT_BIT_CLK_SLAVE;
    cfg.frame_clk_freq = SAMPLE_RATE_HZ;
    cfg.block_size     = BLOCK_SIZE;
    cfg.timeout        = TIMEOUT_MS;
    cfg.mem_slab       = &i2s_tx_slab;

    ret = i2s_configure(i2s_dev, I2S_DIR_TX, &cfg);
    if (ret < 0) 
    {
        printk("I2S config failed\n");
        return ret;
    }

    printk("Start streaming\n");

/* Prefill */
    // for (int i = 0; i < 30; i++)
    // {
    //     void *block;
    //     if (k_mem_slab_alloc(&i2s_tx_slab, &block, K_NO_WAIT) == 0)
    //     {
    //         fill_block((int16_t *)block);
    //         i2s_buf_write(i2s_dev, block, BLOCK_SIZE);
    //     }
    // }

    // /* Start DMA */
    // i2s_trigger(i2s_dev, I2S_DIR_TX, I2S_TRIGGER_START);

    // /* Create REALTIME audio thread */
    // k_thread_create(&audio_thread,
    //                 audio_stack,
    //                 K_THREAD_STACK_SIZEOF(audio_stack),
    //                 audio_thread_fn,
    //                 NULL, NULL, NULL,
    //                 AUDIO_THREAD_PRIO,
    //                 0,
    //                 K_NO_WAIT);


    //prefill
    for (int i = 0; i < 30; i++)
    {
        void *block;
        k_mem_slab_alloc(&i2s_tx_slab, &block, K_FOREVER);
        fill_block((int16_t *)block);
        i2s_buf_write(i2s_dev, block, BLOCK_SIZE);
    }

    ret = i2s_trigger(i2s_dev, I2S_DIR_TX, I2S_TRIGGER_START);
    if (ret < 0) 
    {
        printk("I2S trigger failed\n");
        return ret;
    }

    while (1)
    {
        void *block;

        ret = k_mem_slab_alloc(&i2s_tx_slab, &block, K_FOREVER);
       
        if (ret < 0)
        {
           printk("Slab alloc failed\n");
           k_sleep(K_USEC(30));
           continue;
        }

        fill_block((int16_t *)block);
       
        ret = i2s_buf_write(i2s_dev, block, BLOCK_SIZE);
     
        if (ret == -ENOMEM)
        {
            /* Queue full — try again */
            k_mem_slab_free(&i2s_tx_slab, block);
            printk("free=%d\n", k_mem_slab_num_free_get(&i2s_tx_slab));
            continue;
        }
        else if (ret < 0)
        {
            printk("I2S error %d\n", ret);
            i2s_trigger(i2s_dev, I2S_DIR_TX, I2S_TRIGGER_DROP);
            k_sleep(K_MSEC(5));
            i2s_trigger(i2s_dev, I2S_DIR_TX, I2S_TRIGGER_PREPARE);
            k_sleep(K_MSEC(2));
            i2s_trigger(i2s_dev, I2S_DIR_TX, I2S_TRIGGER_START);
            k_mem_slab_free(&i2s_tx_slab, block);
            printk("free=%d\n", k_mem_slab_num_free_get(&i2s_tx_slab));
            continue;
        }
    }

   
}


and codec file 
codec.c

#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include "codec.h"
#include <zephyr/drivers/pwm.h>


#define CODEC_ADDR 0x18 // i2c slave adress
#define RESET_NODE DT_NODELABEL(led0)  // reset pin node

#define PWM_PERIOD_NS 250U   // 4 MHz
#define PWM_PULSE_NS  125U   // 50% duty

const struct gpio_dt_spec codec_reset_pin = GPIO_DT_SPEC_GET(DT_NODELABEL(codec_reset), gpios); // for reset pin

static const struct i2c_dt_spec dev_i2c = I2C_DT_SPEC_GET(DT_NODELABEL(audiocodec));    // i2c device tree

static const struct pwm_dt_spec pwm_led0 = PWM_DT_SPEC_GET(DT_ALIAS(pwm_led0));       //    pwm device tree


/**
 * Register declaration
 */

const register_value REGISTER_DATA[] = {
//			# reg[0][0]   = 0x00   ; Select Page 0
{0,0x00},          // Select Page 0

/* Software reset */
{1,0x01},

/* ---------- PLL CONFIG (MCLK = 4 MHz → 8 kHz Fs) ---------- */
{4,0x03},          // PLL input = MCLK, CODEC_CLK = PLL
{5,0xD4},          // PLL power up, P=5, R=4   D4
{6,0x20},          // J=32
{7,0x00},          // D MSB
{8,0x00},          // D LSB

      // *** PLL LOCK WAIT (VERY IMPORTANT) ***

/* ---------- I2S DIGITAL ---------- */
{27,0x0C},         // I2S, 16bit, slave 0C

/* ---------- DAC CLOCK TREE ---------- */
{11,0x84},         // NDAC=4, power up
{12,0x99},         // MDAC=25, power up
{14,0x80},         // DOSR=128 → Fs = 8kHz
{29,0x01},         // DAC clock source  0x01
{30,0x84},         // BCLK divider  84

{60,0x00},   // Disable miniDSP, DAC input from serial port
{61,0x00},

/* ---------- DAC POWER / UNMUTE ---------- */
{63,0xD6},         // Soft stepping  D4
{64,0x00},         // Left DAC unmutes
{65,0x00},         // Right DAC unmute
{66,0x00},         // DAC volume 00 dB


// {71,0x82},    // beep
// {72,0x82},
// {81,0x80},
// {82,0x00},
// {83,0x00},

/* ===================================================== */
/* ===================== PAGE 1 ========================= */
/* ===================================================== */

{0,0x01},          // Select Page 1

/* ---------- Analog Power ---------- */
{30,0x00},         // Analog blocks power control
{31,0xC0},         // HPL + HPR unmute
{32,0xC6},         // Speaker drivers power up

/* ---------- DAC → Headphone ---------- */
{35,0xA8},         // Route DAC L/R → HP
{36,0x80},         // HP volume 0 dB
{37,0x80},         // HP volume 0 dB

/* ---------- Speaker ---------- */
{34,0x30},         // Speaker path enable
{42,0x3D},         // Speaker gain 1D
{43,0x3D},         // Speaker gain 1D
{44,0xC0},         // Speaker unmute

/* ---------- Route DAC → Speaker ---------- */
{38,0x80},
{39,0x80},

/* ---------- MIC (optional) ---------- */
{46,0x00},         // MICBIAS 2.5V 0x0A
{47,0x00},         // MIC gain
{48,0x00},        //0x40
{49,0x00},        //0x40
 
};


const register_value REGISTER_DATA[];


static const struct gpio_dt_spec rst = GPIO_DT_SPEC_GET(RESET_NODE, gpios); // for reset pin

const size_t REGISTER_LEN = sizeof(REGISTER_DATA) / sizeof(register_value);  // length of register data

uint32_t cfg = I2C_MODE_CONTROLLER | I2C_SPEED_SET(I2C_SPEED_STANDARD); // configration of i2c


/**
 * @brief codec_i2c_write
 * @param
 * device tree
 * adress
 * buffer
 * length of message
 */
static int codec_i2c_write(const struct device *dev,
                           uint8_t addr, uint8_t *buf, uint32_t len)
{
    struct i2c_msg msg = {
        .buf = buf,
        .len = len,
        .flags = I2C_MSG_WRITE | I2C_MSG_STOP,
    };

    return i2c_transfer(dev, &msg, 1, addr);
}
/**
 *brief codec_i2c_write_read
    *param device tree
    *param address
    *param write buffer
    *param number of bytes to write
    *param read buffer
    *param number of bytes to read
 */
static int codec_i2c_write_read(const struct device *dev,
                                uint16_t addr,
                                const void *write_buf, size_t num_write,
                                void *read_buf, size_t num_read)
{

    struct i2c_msg msg[2];
    msg[0].buf = (uint8_t *)write_buf;
    msg[0].len = num_write;
    msg[0].flags = I2C_MSG_WRITE;

    msg[1].buf = (uint8_t *)read_buf;
    msg[1].len = num_read;
    msg[1].flags = I2C_MSG_READ | I2C_MSG_STOP;
    return i2c_write_read_dt(dev, write_buf, num_write, read_buf, num_read); // perform i2c write read
}


/*
brief codec_reset_pulse
param none
*/
int codec_reset_pulse(void)
{
    int ret;

    ret = gpio_pin_set_dt(&codec_reset_pin, 1); // LOW → reset active

    k_msleep(10); /* HIGH → reset released */

    ret = gpio_pin_set_dt(&codec_reset_pin, 0); // HIGH → reset released

    k_msleep(20);

    return ret;
}

/**
 * brief codec_write_register
 * param page
 * param reg
 * param val
 */
static int codec_write_register(uint8_t page, uint8_t reg, uint8_t val)
{
    static uint8_t last_page = 0xFF; // invalid page at start
    uint8_t tx_buf[2]; // transmit buffer
    uint8_t rx_buf[2];  // receive buffer
    int err;

    /* Only update page register if page actually changed */
    if (page != last_page)
    {
        tx_buf[0] = 0x00; // Page Select Register
        tx_buf[1] = page; // New Page Number

        err =codec_i2c_write_read(&dev_i2c, CODEC_ADDR, tx_buf, 2, rx_buf, 2); // write page select register
        if (err)
        {
            printk("I2C: page switch failed (page=%u) err=%d\n", page, err); // log error
            return err;
        }

        last_page = page; // update page tracking
        k_msleep(1);      // small delay for codec stability
    }

    /* Now write the actual register */
    tx_buf[0] = reg;
    tx_buf[1] = val;

    err =codec_i2c_write_read(&dev_i2c, CODEC_ADDR, tx_buf, 2, rx_buf, 2); // write register
    if (err)
    {
         printk("[PAGE %u] REG 0x%02X <= 0x%02X  \n",
           page, reg, val);
    }

    return err;
}

/**
 * brief codec_write_table
 * param table
 * param length of table
 */

static int codec_write_table(const register_value *table, size_t len)
{
    uint8_t current_page = 0x00; // start on page 0
    int err;

    for (size_t i = 0; i < len; i++)
    {
        uint8_t reg = table[i].reg_no;  // register number
        uint8_t val = table[i].reg_value;  // register value

        /* Page change */
        if (reg == 0x00)
        {
            uint8_t new_page = val; // new page number

            /* Always change page through page 0 register 0 */
            err = codec_write_register(0x00, 0x00, new_page);   // write page select register
            if (err)
            {
                return err;
            }
            current_page = new_page;  // update current page
            k_msleep(1);  //    small delay for codec stability
            continue;
        }

        /* Normal register write on current page */
        err = codec_write_register(current_page, reg, val);

        printk("reg=0x%02X val=0x%02X err=%d\n", reg, val, err);
        if (err)
        {
            return err;
        }
        k_msleep(1);
    }

    return 0;
}

/**
 *brief codec_probe
 param none
 */
static bool codec_probe(void)
{
    uint8_t reg0 = 0x00;
    uint8_t read_back = 0;

    int err = codec_i2c_write_read(&dev_i2c, CODEC_ADDR, &reg0, 1, &read_back, 1); // write and read reg 0
    if (err)
    {
        printk("I2C probe failed err=%d\n", err);
        return false;
    }

    printk("Codec responded: reg0 = 0x%02X\n", read_back); //   log reg 0 value

    return true;
}

/*
brief codec_i2c_config
param none
*/
static int codec_i2c_config(void)
{
    if (!device_is_ready(dev_i2c.bus)) //   check i2c bus ready
    {
        printk("Error: I2C bus %s is not ready!\n", dev_i2c.bus->name);
        return -1;
    }

    printk("I2C bus ready, addr=0x%02x\n", dev_i2c.addr);  //   log i2c bus ready

    return 0;
}


//pwm 4mhz generation 

/*
brief pwm_4mhz
param none
*/
int pwm_4mhz()
{
    int ret;

    if (!pwm_is_ready_dt(&pwm_led0)) // check pwm device ready
    {
        printk("PWM device not ready\n");
        return 0;
    }

    ret = pwm_set_dt(&pwm_led0, PWM_PERIOD_NS, PWM_PULSE_NS); // configure pwm for 4 MHz
    if (ret)
    {
        printk("PWM cannot generate 4 MHz (ret=%d)\n", ret);
        return -1; // Some error code
    }

    printk("PWM configured: period=%dns pulse=%dns\n", PWM_PERIOD_NS, PWM_PULSE_NS);

    return ret;
}

/*
brief codec_gpios_config
param none
*/
static int codec_gpios_config(void)
{
    int ret;

    if (!gpio_is_ready_dt(&codec_reset_pin)) // check reset pin ready
    {
        printk("Error: Codec reset pin not ready\n");
        return -1;
    }

    ret = gpio_pin_configure_dt(&codec_reset_pin,
                                GPIO_OUTPUT_ACTIVE | GPIO_ACTIVE_LOW); // configure reset pin
    if (ret < 0)
    {
        printk("Error %d: Failed to configure codec reset pin\n", ret);
        return -1;
    }

    return 0;
}

/*
brief i2c_init_codec
param none
 */
int i2c_init_codec()
{
    int err;

    int ret;

    ret = codec_gpios_config(); // codec gpio config
    if (ret != 0)               //    check gpio config error
    {
        return ret;
    }

    k_msleep(20);

    if (!device_is_ready(dev_i2c.bus)) // check i2c bus ready
    {
        printk("I2C bus %s is not ready!\n", dev_i2c.bus->name);
        return -1;
    }

    k_msleep(20);

    printk("I2C bus ready, addr=0x%02x\n",dev_i2c.addr);

    // reset pin config
    codec_reset_pulse();

    /*codec address check*/
    if (!codec_probe())
    {
        printk("Codec not found on I2C address 0x%02X\n", CODEC_ADDR);
        return -EIO;
    }
   //  k_msleep(20);
    printk("Writing codec register table...\n");

    err = codec_write_table(REGISTER_DATA, REGISTER_LEN); // write codec register table
    if (err)
    {
        printk("Codec register table FAILED: %d\n", err);
        return err;
    }

    k_msleep(20);

    printk("Codec init DONE.\n");

    printk("I2C ready\n");
    return 0;
}



Overlay file 


&pinctrl {
 
   i2s20_default: i2s20_default {
		group1 {
        psels = <
            NRF_PSEL(I2S_SDOUT, 1, 7)
            NRF_PSEL(I2S_SDIN,  1, 6)
            NRF_PSEL(I2S_SCK,   1, 4)
            NRF_PSEL(I2S_LRCK,  1, 5)
           NRF_PSEL(I2S_MCK,   1, 8)
        >;
        };
	};

	i2s20_sleep: i2s20_sleep {
		group1 {
        psels = <
            NRF_PSEL(I2S_SDOUT, 1, 7)
            NRF_PSEL(I2S_SDIN,  1, 6)
            NRF_PSEL(I2S_SCK,   1, 4)
            NRF_PSEL(I2S_LRCK,  1, 5)
            NRF_PSEL(I2S_MCK,   1, 8) 
        >;
        
			low-power-enable;
		};
	};

    i2c21_default: i2c21_default {
        group1 {
            psels =
                    <NRF_PSEL(TWIM_SCL, 1, 12)>,
                    <NRF_PSEL(TWIM_SDA, 1, 13)>;
                    bias-pull-up;
                   
        };
    };

    i2c21_sleep: i2c21_sleep {
        group1 {
            psels = <NRF_PSEL(TWIM_SCL, 1, 12)>,
                    <NRF_PSEL(TWIM_SDA, 1, 13)>;
                    low-power-enable;
        };
    };

	
	pwm20_default: pwm20_default {
		group1 {
				psels = <NRF_PSEL(PWM_OUT0, 1, 11)>;
		};
	};

	pwm20_sleep: pwm20_sleep {
		group1 {
				psels = <NRF_PSEL(PWM_OUT0, 1, 11)>;
			low-power-enable;
		};
	};
};


/ {
	model = "ISC54L15 EVK (Custom)";
	compatible = "nordic,nrf54l15-cpuapp";

	chosen {
		zephyr,console = &uart20;
		zephyr,shell-uart = &uart20;
		zephyr,uart-mcumgr = &uart20;
		zephyr,bt-c2h-uart = &audiocodec;
		zephyr,bt-hci = &audiocodec;
		zephyr,bt-mon-uart = &audiocodec;
		zephyr,code-partition = &audiocodec;
	};

	custom_pins {
		compatible = "gpio-keys";

		codec_reset: codec_reset {
			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
			label = "Codec Reset";
		};
	};

	leds {
		compatible = "gpio-leds";

		led0: led_0 {
			gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
			label = "User LED 0";
		};

		led1: led_1 {
			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
			label = "PWM LED 1";
		};
	};

	pwmleds {
		compatible = "pwm-leds";

		pwm_led0: pwm_led0 {
			pwms = <&pwm20 0 PWM_USEC(1) PWM_POLARITY_NORMAL>;
		};
	};
};

&i2s20 {
	pinctrl-0 = <&i2s20_default>;
	pinctrl-names = "default";
	status = "okay";
	zephyr,pm-device-runtime-auto;
};

&i2c21{

    compatible = "nordic,nrf-twim";
    pinctrl-0 = <&i2c21_default>;
    pinctrl-1 = <&i2c21_sleep>;
    pinctrl-names = "default", "sleep";

    audiocodec: audiocodec@18 {
        compatible = "i2c-device";
        status = "okay";
        reg = < 0x18 >;
    };

};



&gpio0 {
	status = "okay";
};


// &led0 {
// 	gpios = <&gpio1 9 0>;
// };

&pwm20 {
	status = "okay";
	pinctrl-0 = <&pwm20_default>;
	pinctrl-1 = <&pwm20_sleep>;
	pinctrl-names = "default", "sleep";
};

/*
 * Codec-style I2S SLAVE playback using k_mem_slab
 * nRF54Lx DK
 */

#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/i2s.h>
#include <zephyr/sys/printk.h>
#include "codec/codec.h"

#define I2S_NODE DT_NODELABEL(i2s20)

//audio
#define SAMPLE_RATE_HZ     8000
#define SAMPLE_BIT_WIDTH   16
#define CHANNELS           2
#define SAMPLES_PER_BLOCK  160
//#define SAMPLES_PER_BLOCK  (SAMPLE_RATE_HZ / 10)    // 33ms blocks
#define BLOCK_SIZE         (SAMPLES_PER_BLOCK * CHANNELS * sizeof(int16_t))
#define NUM_BLOCKS         120
#define TIMEOUT_MS         2000

// #define AUDIO_THREAD_STACK 2048
// #define AUDIO_THREAD_PRIO  -2   

// K_THREAD_STACK_DEFINE(audio_stack, AUDIO_THREAD_STACK);
// static struct k_thread audio_thread;



// K_THREAD_STACK_DEFINE(i2s_stack, I2S_THREAD_STACK);
// static struct k_thread i2s_thread_data;

static const struct device *i2s_dev = DEVICE_DT_GET(I2S_NODE);

//  memory slab for I2S TX buffers
K_MEM_SLAB_DEFINE(i2s_tx_slab, BLOCK_SIZE, NUM_BLOCKS, 4);

//sine
// static int16_t sine_lut[] = {
//     3211, 6392, 9511, 12539, 15446, 18204, 20787, 23169,
//     25329, 27244, 28897, 30272, 31356, 32137, 32609, 32767,
//     -3212, -6393, -9512, -12540, -15447, -18205, -20788, -23170,
//     -25330, -27245, -28898, -30273, -31357, -32138, -32610, -32767};


static int16_t sine_lut[] = {
    6392,  12539,  18204,  23169,  27244,  30272,  32137,  32767,  32137,
    30272, 27244, 23169, 18204, 12539, 6392, 0, -6393, -12540,
    -18205, -23170, -27245, -30273, -32138, -32767, -32138, -30273, -27245,
    -23170, -18205, -12540, -6393, -1};

// static int16_t sine_lut[8] = {
//      0,
//  23170,
//  32767,
//  23170,
//      0,
// -23170,
// -32768,
// -23170
// };


// Fill block
static void fill_block(int16_t *buf)
{
    int lut_len = ARRAY_SIZE(sine_lut);

    for (int i = 0; i < SAMPLES_PER_BLOCK; i++)
    {
        int16_t s = sine_lut[i % lut_len];
        buf[2 * i] = s;
        buf[2 * i + 1] = s;
        // buf[i] = 28000;
    }
}

// // thread creation
// void audio_thread_fn(void *a, void *b, void *c)
// {
//     while (1)
//     {
//         void *block;
//         int ret;

//         ret = k_mem_slab_alloc(&i2s_tx_slab, &block, K_NO_WAIT);
//         if (ret != 0)
//         {
//             k_yield();   // allow DMA + ISR
//             continue;
//         }

//         fill_block((int16_t *)block);

//         ret = i2s_buf_write(i2s_dev, block, BLOCK_SIZE);

//         if (ret == -ENOMEM)
//         {
//             k_mem_slab_free(&i2s_tx_slab, block);
//         }
//         else if (ret < 0)
//         {
//             printk("I2S error %d\n", ret);
//             k_mem_slab_free(&i2s_tx_slab, block);
//         }
//     }
// }



int main(void)
{
    struct i2s_config cfg;
    int ret;

    printk("I2S playback (mem_slab)\n");

    // clocking and codec init
    ret = pwm_4mhz();
    if (ret < 0)
    {
        printk("PWM init failed\n");
        return ret;
    }

    for (int i = 0; i < 20; i++)
    {
        ret = i2c_init_codec();
        if (ret == 0)
        {
            break;
        }
        k_msleep(5);
    }
    if (ret < 0)
    {
        printk("Codec init failed\n");
        return ret;
    }

    k_msleep(10);
    // printk("BLOCK=%d  SAMPLES=%d\n", BLOCK_SIZE, SAMPLES_PER_BLOCK);

    if (!device_is_ready(i2s_dev))
    {
        printk("I2S not ready\n");
        return -ENODEV;
    }

    // I2S CONFIG
    cfg.word_size      = SAMPLE_BIT_WIDTH;
    cfg.channels       = CHANNELS;
    cfg.format         =I2S_FMT_DATA_FORMAT_I2S;;   //cfg.format = I2S_FMT_DATA_FORMAT_LEFT_JUSTIFIED;

    cfg.options        = I2S_OPT_FRAME_CLK_SLAVE |
                         I2S_OPT_BIT_CLK_SLAVE;
    cfg.frame_clk_freq = SAMPLE_RATE_HZ;
    cfg.block_size     = BLOCK_SIZE;
    cfg.timeout        = TIMEOUT_MS;
    cfg.mem_slab       = &i2s_tx_slab;

    ret = i2s_configure(i2s_dev, I2S_DIR_TX, &cfg);
    if (ret < 0) 
    {
        printk("I2S config failed\n");
        return ret;
    }

    printk("Start streaming\n");

/* Prefill */
    // for (int i = 0; i < 30; i++)
    // {
    //     void *block;
    //     if (k_mem_slab_alloc(&i2s_tx_slab, &block, K_NO_WAIT) == 0)
    //     {
    //         fill_block((int16_t *)block);
    //         i2s_buf_write(i2s_dev, block, BLOCK_SIZE);
    //     }
    // }

    // /* Start DMA */
    // i2s_trigger(i2s_dev, I2S_DIR_TX, I2S_TRIGGER_START);

    // /* Create REALTIME audio thread */
    // k_thread_create(&audio_thread,
    //                 audio_stack,
    //                 K_THREAD_STACK_SIZEOF(audio_stack),
    //                 audio_thread_fn,
    //                 NULL, NULL, NULL,
    //                 AUDIO_THREAD_PRIO,
    //                 0,
    //                 K_NO_WAIT);


    //prefill
    for (int i = 0; i < 30; i++)
    {
        void *block;
        k_mem_slab_alloc(&i2s_tx_slab, &block, K_FOREVER);
        fill_block((int16_t *)block);
        i2s_buf_write(i2s_dev, block, BLOCK_SIZE);
    }

    ret = i2s_trigger(i2s_dev, I2S_DIR_TX, I2S_TRIGGER_START);
    if (ret < 0) 
    {
        printk("I2S trigger failed\n");
        return ret;
    }

    while (1)
    {
        void *block;

        ret = k_mem_slab_alloc(&i2s_tx_slab, &block, K_FOREVER);
       
        if (ret < 0)
        {
           printk("Slab alloc failed\n");
           k_sleep(K_USEC(30));
           continue;
        }

        fill_block((int16_t *)block);
       
        ret = i2s_buf_write(i2s_dev, block, BLOCK_SIZE);
     
        if (ret == -ENOMEM)
        {
            /* Queue full — try again */
            k_mem_slab_free(&i2s_tx_slab, block);
            printk("free=%d\n", k_mem_slab_num_free_get(&i2s_tx_slab));
            continue;
        }
        else if (ret < 0)
        {
            printk("I2S error %d\n", ret);
            i2s_trigger(i2s_dev, I2S_DIR_TX, I2S_TRIGGER_DROP);
            k_sleep(K_MSEC(5));
            i2s_trigger(i2s_dev, I2S_DIR_TX, I2S_TRIGGER_PREPARE);
            k_sleep(K_MSEC(2));
            i2s_trigger(i2s_dev, I2S_DIR_TX, I2S_TRIGGER_START);
            k_mem_slab_free(&i2s_tx_slab, block);
            printk("free=%d\n", k_mem_slab_num_free_get(&i2s_tx_slab));
            continue;
        }
    }

   
}


and codec file 
codec.c

#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include "codec.h"
#include <zephyr/drivers/pwm.h>


#define CODEC_ADDR 0x18 // i2c slave adress
#define RESET_NODE DT_NODELABEL(led0)  // reset pin node

#define PWM_PERIOD_NS 250U   // 4 MHz
#define PWM_PULSE_NS  125U   // 50% duty

const struct gpio_dt_spec codec_reset_pin = GPIO_DT_SPEC_GET(DT_NODELABEL(codec_reset), gpios); // for reset pin

static const struct i2c_dt_spec dev_i2c = I2C_DT_SPEC_GET(DT_NODELABEL(audiocodec));    // i2c device tree

static const struct pwm_dt_spec pwm_led0 = PWM_DT_SPEC_GET(DT_ALIAS(pwm_led0));       //    pwm device tree


/**
 * Register declaration
 */

const register_value REGISTER_DATA[] = {
//			# reg[0][0]   = 0x00   ; Select Page 0
{0,0x00},          // Select Page 0

/* Software reset */
{1,0x01},

/* ---------- PLL CONFIG (MCLK = 4 MHz → 8 kHz Fs) ---------- */
{4,0x03},          // PLL input = MCLK, CODEC_CLK = PLL
{5,0xD4},          // PLL power up, P=5, R=4   D4
{6,0x20},          // J=32
{7,0x00},          // D MSB
{8,0x00},          // D LSB

      // *** PLL LOCK WAIT (VERY IMPORTANT) ***

/* ---------- I2S DIGITAL ---------- */
{27,0x0C},         // I2S, 16bit, slave 0C

/* ---------- DAC CLOCK TREE ---------- */
{11,0x84},         // NDAC=4, power up
{12,0x99},         // MDAC=25, power up
{14,0x80},         // DOSR=128 → Fs = 8kHz
{29,0x01},         // DAC clock source  0x01
{30,0x84},         // BCLK divider  84

{60,0x00},   // Disable miniDSP, DAC input from serial port
{61,0x00},

/* ---------- DAC POWER / UNMUTE ---------- */
{63,0xD6},         // Soft stepping  D4
{64,0x00},         // Left DAC unmutes
{65,0x00},         // Right DAC unmute
{66,0x00},         // DAC volume 00 dB


// {71,0x82},    // beep
// {72,0x82},
// {81,0x80},
// {82,0x00},
// {83,0x00},

/* ===================================================== */
/* ===================== PAGE 1 ========================= */
/* ===================================================== */

{0,0x01},          // Select Page 1

/* ---------- Analog Power ---------- */
{30,0x00},         // Analog blocks power control
{31,0xC0},         // HPL + HPR unmute
{32,0xC6},         // Speaker drivers power up

/* ---------- DAC → Headphone ---------- */
{35,0xA8},         // Route DAC L/R → HP
{36,0x80},         // HP volume 0 dB
{37,0x80},         // HP volume 0 dB

/* ---------- Speaker ---------- */
{34,0x30},         // Speaker path enable
{42,0x3D},         // Speaker gain 1D
{43,0x3D},         // Speaker gain 1D
{44,0xC0},         // Speaker unmute

/* ---------- Route DAC → Speaker ---------- */
{38,0x80},
{39,0x80},

/* ---------- MIC (optional) ---------- */
{46,0x00},         // MICBIAS 2.5V 0x0A
{47,0x00},         // MIC gain
{48,0x00},        //0x40
{49,0x00},        //0x40
 
};


const register_value REGISTER_DATA[];


static const struct gpio_dt_spec rst = GPIO_DT_SPEC_GET(RESET_NODE, gpios); // for reset pin

const size_t REGISTER_LEN = sizeof(REGISTER_DATA) / sizeof(register_value);  // length of register data

uint32_t cfg = I2C_MODE_CONTROLLER | I2C_SPEED_SET(I2C_SPEED_STANDARD); // configration of i2c


/**
 * @brief codec_i2c_write
 * @param
 * device tree
 * adress
 * buffer
 * length of message
 */
static int codec_i2c_write(const struct device *dev,
                           uint8_t addr, uint8_t *buf, uint32_t len)
{
    struct i2c_msg msg = {
        .buf = buf,
        .len = len,
        .flags = I2C_MSG_WRITE | I2C_MSG_STOP,
    };

    return i2c_transfer(dev, &msg, 1, addr);
}
/**
 *brief codec_i2c_write_read
    *param device tree
    *param address
    *param write buffer
    *param number of bytes to write
    *param read buffer
    *param number of bytes to read
 */
static int codec_i2c_write_read(const struct device *dev,
                                uint16_t addr,
                                const void *write_buf, size_t num_write,
                                void *read_buf, size_t num_read)
{

    struct i2c_msg msg[2];
    msg[0].buf = (uint8_t *)write_buf;
    msg[0].len = num_write;
    msg[0].flags = I2C_MSG_WRITE;

    msg[1].buf = (uint8_t *)read_buf;
    msg[1].len = num_read;
    msg[1].flags = I2C_MSG_READ | I2C_MSG_STOP;
    return i2c_write_read_dt(dev, write_buf, num_write, read_buf, num_read); // perform i2c write read
}


/*
brief codec_reset_pulse
param none
*/
int codec_reset_pulse(void)
{
    int ret;

    ret = gpio_pin_set_dt(&codec_reset_pin, 1); // LOW → reset active

    k_msleep(10); /* HIGH → reset released */

    ret = gpio_pin_set_dt(&codec_reset_pin, 0); // HIGH → reset released

    k_msleep(20);

    return ret;
}

/**
 * brief codec_write_register
 * param page
 * param reg
 * param val
 */
static int codec_write_register(uint8_t page, uint8_t reg, uint8_t val)
{
    static uint8_t last_page = 0xFF; // invalid page at start
    uint8_t tx_buf[2]; // transmit buffer
    uint8_t rx_buf[2];  // receive buffer
    int err;

    /* Only update page register if page actually changed */
    if (page != last_page)
    {
        tx_buf[0] = 0x00; // Page Select Register
        tx_buf[1] = page; // New Page Number

        err =codec_i2c_write_read(&dev_i2c, CODEC_ADDR, tx_buf, 2, rx_buf, 2); // write page select register
        if (err)
        {
            printk("I2C: page switch failed (page=%u) err=%d\n", page, err); // log error
            return err;
        }

        last_page = page; // update page tracking
        k_msleep(1);      // small delay for codec stability
    }

    /* Now write the actual register */
    tx_buf[0] = reg;
    tx_buf[1] = val;

    err =codec_i2c_write_read(&dev_i2c, CODEC_ADDR, tx_buf, 2, rx_buf, 2); // write register
    if (err)
    {
         printk("[PAGE %u] REG 0x%02X <= 0x%02X  \n",
           page, reg, val);
    }

    return err;
}

/**
 * brief codec_write_table
 * param table
 * param length of table
 */

static int codec_write_table(const register_value *table, size_t len)
{
    uint8_t current_page = 0x00; // start on page 0
    int err;

    for (size_t i = 0; i < len; i++)
    {
        uint8_t reg = table[i].reg_no;  // register number
        uint8_t val = table[i].reg_value;  // register value

        /* Page change */
        if (reg == 0x00)
        {
            uint8_t new_page = val; // new page number

            /* Always change page through page 0 register 0 */
            err = codec_write_register(0x00, 0x00, new_page);   // write page select register
            if (err)
            {
                return err;
            }
            current_page = new_page;  // update current page
            k_msleep(1);  //    small delay for codec stability
            continue;
        }

        /* Normal register write on current page */
        err = codec_write_register(current_page, reg, val);

        printk("reg=0x%02X val=0x%02X err=%d\n", reg, val, err);
        if (err)
        {
            return err;
        }
        k_msleep(1);
    }

    return 0;
}

/**
 *brief codec_probe
 param none
 */
static bool codec_probe(void)
{
    uint8_t reg0 = 0x00;
    uint8_t read_back = 0;

    int err = codec_i2c_write_read(&dev_i2c, CODEC_ADDR, &reg0, 1, &read_back, 1); // write and read reg 0
    if (err)
    {
        printk("I2C probe failed err=%d\n", err);
        return false;
    }

    printk("Codec responded: reg0 = 0x%02X\n", read_back); //   log reg 0 value

    return true;
}

/*
brief codec_i2c_config
param none
*/
static int codec_i2c_config(void)
{
    if (!device_is_ready(dev_i2c.bus)) //   check i2c bus ready
    {
        printk("Error: I2C bus %s is not ready!\n", dev_i2c.bus->name);
        return -1;
    }

    printk("I2C bus ready, addr=0x%02x\n", dev_i2c.addr);  //   log i2c bus ready

    return 0;
}


//pwm 4mhz generation 

/*
brief pwm_4mhz
param none
*/
int pwm_4mhz()
{
    int ret;

    if (!pwm_is_ready_dt(&pwm_led0)) // check pwm device ready
    {
        printk("PWM device not ready\n");
        return 0;
    }

    ret = pwm_set_dt(&pwm_led0, PWM_PERIOD_NS, PWM_PULSE_NS); // configure pwm for 4 MHz
    if (ret)
    {
        printk("PWM cannot generate 4 MHz (ret=%d)\n", ret);
        return -1; // Some error code
    }

    printk("PWM configured: period=%dns pulse=%dns\n", PWM_PERIOD_NS, PWM_PULSE_NS);

    return ret;
}

/*
brief codec_gpios_config
param none
*/
static int codec_gpios_config(void)
{
    int ret;

    if (!gpio_is_ready_dt(&codec_reset_pin)) // check reset pin ready
    {
        printk("Error: Codec reset pin not ready\n");
        return -1;
    }

    ret = gpio_pin_configure_dt(&codec_reset_pin,
                                GPIO_OUTPUT_ACTIVE | GPIO_ACTIVE_LOW); // configure reset pin
    if (ret < 0)
    {
        printk("Error %d: Failed to configure codec reset pin\n", ret);
        return -1;
    }

    return 0;
}

/*
brief i2c_init_codec
param none
 */
int i2c_init_codec()
{
    int err;

    int ret;

    ret = codec_gpios_config(); // codec gpio config
    if (ret != 0)               //    check gpio config error
    {
        return ret;
    }

    k_msleep(20);

    if (!device_is_ready(dev_i2c.bus)) // check i2c bus ready
    {
        printk("I2C bus %s is not ready!\n", dev_i2c.bus->name);
        return -1;
    }

    k_msleep(20);

    printk("I2C bus ready, addr=0x%02x\n",dev_i2c.addr);

    // reset pin config
    codec_reset_pulse();

    /*codec address check*/
    if (!codec_probe())
    {
        printk("Codec not found on I2C address 0x%02X\n", CODEC_ADDR);
        return -EIO;
    }
   //  k_msleep(20);
    printk("Writing codec register table...\n");

    err = codec_write_table(REGISTER_DATA, REGISTER_LEN); // write codec register table
    if (err)
    {
        printk("Codec register table FAILED: %d\n", err);
        return err;
    }

    k_msleep(20);

    printk("Codec init DONE.\n");

    printk("I2C ready\n");
    return 0;
}



Overlay file 


&pinctrl {
 
   i2s20_default: i2s20_default {
		group1 {
        psels = <
            NRF_PSEL(I2S_SDOUT, 1, 7)
            NRF_PSEL(I2S_SDIN,  1, 6)
            NRF_PSEL(I2S_SCK,   1, 4)
            NRF_PSEL(I2S_LRCK,  1, 5)
           NRF_PSEL(I2S_MCK,   1, 8)
        >;
        };
	};

	i2s20_sleep: i2s20_sleep {
		group1 {
        psels = <
            NRF_PSEL(I2S_SDOUT, 1, 7)
            NRF_PSEL(I2S_SDIN,  1, 6)
            NRF_PSEL(I2S_SCK,   1, 4)
            NRF_PSEL(I2S_LRCK,  1, 5)
            NRF_PSEL(I2S_MCK,   1, 8) 
        >;
        
			low-power-enable;
		};
	};

    i2c21_default: i2c21_default {
        group1 {
            psels =
                    <NRF_PSEL(TWIM_SCL, 1, 12)>,
                    <NRF_PSEL(TWIM_SDA, 1, 13)>;
                    bias-pull-up;
                   
        };
    };

    i2c21_sleep: i2c21_sleep {
        group1 {
            psels = <NRF_PSEL(TWIM_SCL, 1, 12)>,
                    <NRF_PSEL(TWIM_SDA, 1, 13)>;
                    low-power-enable;
        };
    };

	
	pwm20_default: pwm20_default {
		group1 {
				psels = <NRF_PSEL(PWM_OUT0, 1, 11)>;
		};
	};

	pwm20_sleep: pwm20_sleep {
		group1 {
				psels = <NRF_PSEL(PWM_OUT0, 1, 11)>;
			low-power-enable;
		};
	};
};


/ {
	model = "ISC54L15 EVK (Custom)";
	compatible = "nordic,nrf54l15-cpuapp";

	chosen {
		zephyr,console = &uart20;
		zephyr,shell-uart = &uart20;
		zephyr,uart-mcumgr = &uart20;
		zephyr,bt-c2h-uart = &audiocodec;
		zephyr,bt-hci = &audiocodec;
		zephyr,bt-mon-uart = &audiocodec;
		zephyr,code-partition = &audiocodec;
	};

	custom_pins {
		compatible = "gpio-keys";

		codec_reset: codec_reset {
			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
			label = "Codec Reset";
		};
	};

	leds {
		compatible = "gpio-leds";

		led0: led_0 {
			gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
			label = "User LED 0";
		};

		led1: led_1 {
			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
			label = "PWM LED 1";
		};
	};

	pwmleds {
		compatible = "pwm-leds";

		pwm_led0: pwm_led0 {
			pwms = <&pwm20 0 PWM_USEC(1) PWM_POLARITY_NORMAL>;
		};
	};
};

&i2s20 {
	pinctrl-0 = <&i2s20_default>;
	pinctrl-names = "default";
	status = "okay";
	zephyr,pm-device-runtime-auto;
};

&i2c21{

    compatible = "nordic,nrf-twim";
    pinctrl-0 = <&i2c21_default>;
    pinctrl-1 = <&i2c21_sleep>;
    pinctrl-names = "default", "sleep";

    audiocodec: audiocodec@18 {
        compatible = "i2c-device";
        status = "okay";
        reg = < 0x18 >;
    };

};



&gpio0 {
	status = "okay";
};


// &led0 {
// 	gpios = <&gpio1 9 0>;
// };

&pwm20 {
	status = "okay";
	pinctrl-0 = <&pwm20_default>;
	pinctrl-1 = <&pwm20_sleep>;
	pinctrl-names = "default", "sleep";
};

RE: Next buffers not supplied on time

Sharon123 — Thu, 19 Feb 2026 15:18:01 GMT

Thanks For the Response.

Next time I should do.

Thanks

RE: Next buffers not supplied on time

Maria Gilje — Thu, 19 Feb 2026 15:02:15 GMT

Hello,

The last error log before the assertion fail indicates that the I2S device is in the stopping state and the I2S driver is also expecting a new buffer.

I have not verified that your sine wave table works as expected, but you could use one of the tone_gen functions from tone.c as a reference for how sample tones can be generated.

In the future, please do the following when posting to DevZone:

Avoid over-use of tagging. Us engineers here at DevZone have a policy to get back to our customers within the next working day. Because of time zones this could mean that you won't get a reply every day. If you don't get a reply every other day and you are in a rush, please notify your RSM and they can inform us internally. Tagging the engineer assigned to your case will not result in a quicker response.
Use the Insert->Code option when sharing code and logs. It is very difficult to cifferentiate between logs, code and other text when everything looks like normal text. I have edited your ticket now to better the readability. The content is unchanged.

Best regards,

Maria

RE: Next buffers not supplied on time

Sharon123 — Thu, 19 Feb 2026 10:49:27 GMT

Menon

RE: Next buffers not supplied on time

Sharon123 — Thu, 19 Feb 2026 03:35:51 GMT

Menon

RE: Next buffers not supplied on time

Sharon123 — Wed, 18 Feb 2026 15:35:32 GMT

Menon

1. my issue is i get " I2S TX all the times shows after some trasmission " No buffet is available" I shared Log with You,

2. I did not get sine wave sound .

3. I check mic input is properly enabled

4. I am use Nrf54l15 -code share above

RE: Next buffers not supplied on time

Sharon123 — Wed, 18 Feb 2026 15:33:08 GMT

Now I am closed

RE: Next buffers not supplied on time

Sharon123 — Wed, 18 Feb 2026 15:32:33 GMT

RE: Next buffers not supplied on time

Menon — Wed, 18 Feb 2026 15:30:33 GMT

Hello,

I’m sure my colleague will get back to you soon. In the meantime, I would kindly ask you to explain the context and the issue in more detail instead of pasting only logs and code. I noticed that the same format was followed in the original ticket as well, and it can be quite difficult for an engineer to review the issue without proper context. I recommend using the Insert option when sharing logs and code, as it makes them easier to read and review.

Sorry, but I need to close this ticket as it is a duplicate. DevZone does not encourage having multiple tickets for the same issue.

Kind Regards,

Abhijith

RE: Next buffers not supplied on time

Sharon123 — Wed, 18 Feb 2026 15:11:13 GMT

@menon I did not get any answer from your collegue, So could you help me

RE: Next buffers not supplied on time

Menon — Wed, 18 Feb 2026 13:57:53 GMT

Hello,

I see that you already have another ticket open for the same issue, and my colleague is currently working on it. Please close this ticket and continue the discussion in the original one.

Please close this ticket as it is a duplicate of: 357350

Also, when posting, please describe the issue and provide some context instead of pasting the entire logs and code directly into the text. You can use the insert option to attach logs and code separately, which makes it much easier for us to review.

Kind Regards,

Abhijith