NRF54L15: DFU to internal flash fails without JLink

RE: NRF54L15: DFU to internal flash fails without JLink

Vidar Berg — Fri, 20 Feb 2026 11:57:33 GMT

Good to hear that it worked. Thank you for taking the time to report back what the issue was.

RE: NRF54L15: DFU to internal flash fails without JLink

Bruno Randolf — Fri, 20 Feb 2026 11:35:19 GMT

You were right, the CS timing was too fast in some cases. Apparently this was more prominent when doing flash writes as well. Moving to triggering CS manually before the transaction on the other MCU solved the problem. Thank you!!!

RE: NRF54L15: DFU to internal flash fails without JLink

Vidar Berg — Fri, 20 Feb 2026 10:14:53 GMT

Yes, it's interesting that it works with BLE. Is the update image staged in external or internal flash in that case?

[quote userid="15175" url="~/f/nordic-q-a/127095/nrf54l15-dfu-to-internal-flash-fails-without-jlink/561668"]The problem comes when I want to access the internal flash thru the DFU target library.[/quote]

What are the symptoms? Did you inspect the memory afterwards to see what was written if anything? Do you have CONFIG_RESET_ON_FATAL_ERRROR disabled to prevent the device from rebooting in case of a runtime error?

RE: NRF54L15: DFU to internal flash fails without JLink

Bruno Randolf — Fri, 20 Feb 2026 09:42:06 GMT

I had to enable CONSTLAT in order for SPIS to work, due to the fact you have pointed out. See NRF54L15 SPIS needs CONSTLAT... That part works well. I can send and receive on the SPI bus. The problem comes when I want to access the internal flash thru the DFU target library.

Another interesting thing to note may be that DFU over BLE works, also without the debugger, using the same code and the DFU target library.

RE: NRF54L15: DFU to internal flash fails without JLink

Vidar Berg — Fri, 20 Feb 2026 06:59:23 GMT

Hello,

Maybe the SPI master is asserting the CS signal too late? In debug interface mode the HF clock is kept running in sleep which reduces the wakeup time of the SPIS peripheral as it doesn't have to wait for the clock to become ready. This effectively shortens the required time between when the CS signal is asserted and transfer start.

Best regards,

Vidar