sQSPI: "High Speed Transfers" drive strength

RE: sQSPI: "High Speed Transfers" drive strength

Kenneth — Tue, 03 Mar 2026 13:57:29 GMT

Hello,

To configure extra high driver for the sqspi you do this in devicetree like this:

&pinctrl {
	sqspi_default: sqspi_default {
		group1 {
			psels = <NRF_PSEL(SDP_MSPI_SCK, 2, 1)>,
				<NRF_PSEL(SDP_MSPI_CS0, 2, 5)>,
				<NRF_PSEL(SDP_MSPI_DQ0, 2, 2)>;
			nordic,drive-mode = <NRF_DRIVE_E0E1>;
		};
		group2 {
			psels = <NRF_PSEL(SDP_MSPI_DQ1, 2, 4)>,
				<NRF_PSEL(SDP_MSPI_DQ2, 2, 3)>,
				<NRF_PSEL(SDP_MSPI_DQ3, 2, 0)>;
			nordic,drive-mode = <NRF_DRIVE_E0E1>;
			bias-pull-up;
		};
	};

	sqspi_sleep: sqspi_sleep {
		group1 {
			low-power-enable;
			psels = <NRF_PSEL(SDP_MSPI_SCK, 2, 1)>,
				<NRF_PSEL(SDP_MSPI_CS0, 2, 5)>,
				<NRF_PSEL(SDP_MSPI_DQ0, 2, 2)>,
				<NRF_PSEL(SDP_MSPI_DQ1, 2, 4)>,
				<NRF_PSEL(SDP_MSPI_DQ2, 2, 3)>,
				<NRF_PSEL(SDP_MSPI_DQ3, 2, 0)>;
		};
	};
};

Even though other pins can in theory also be configured to E0E1, please follow the statement from the documentation that says "...no other peripheral or ETM trace on the P2 port can use the extra-high-drive GPIO configuration. They are limited to using high-drive strength.."

Kenneth

RE: sQSPI: "High Speed Transfers" drive strength

JordanYates — Mon, 23 Feb 2026 00:57:03 GMT

Does that mean that all of the text about the sQSPI requiring exclusive access to the extra-high-drive strength is incorrect? Other peripherals on P2 can also use the E0E1 strength?

RE: sQSPI: "High Speed Transfers" drive strength

runsiv — Fri, 20 Feb 2026 14:56:45 GMT

Update. Drive configuration is done in the DRIVE0/1 fields of the PIN_CNF GPIO register. It's a per-pin register. it does not apply to the entire port.

RE: sQSPI: "High Speed Transfers" drive strength

runsiv — Fri, 20 Feb 2026 10:21:10 GMT

Hi Jordan.
I will check this internally and will update as soon as I hear anything

Regards

Runar