executing small applications from SRAM -- performance implications

RE: executing small applications from SRAM -- performance implications

Einar Thorsrud — Fri, 20 Mar 2026 09:48:21 GMT

Hi,

The RRAM (NVM) is automatically powered down when not used. In the scenario you describe I assume you are in practice executing the whole coremark like test from cache, so RRAM has no practical effect an you are effectively comparing current consumption execution from Cache with execution from RAM, and then the cache is slightly more power efficient.

RE: executing small applications from SRAM -- performance implications

bios-bob — Fri, 20 Mar 2026 04:03:55 GMT

i reviewed my power numbers, and confirmed that running a load similar to coremark actually consumes *more* power when executing out of SRAM vs FLASH/CACHE.... execution time was roughly the same....

any explanation as to why??? and is it possible to "power-down" the FLASH when active???

RE: executing small applications from SRAM -- performance implications

Einar Thorsrud — Mon, 16 Mar 2026 14:05:03 GMT

Hi,l

You are right, the VPR does not have cache. Regarding wait states you are also right. Note that we recommend that the VPR executes code from RAM and not RRAM (though that is also supported).

RE: executing small applications from SRAM -- performance implications

bios-bob — Mon, 16 Mar 2026 13:51:36 GMT

let me relook at my own power numbers -- especially executing from SRAM vs RRAM+CACHE....

looking at your block diagram, it appears the risc-v does *not* have a cache.... even with exclusive access to RRAM, won't the CPU stall when fetching instructions???

does the risc-v have a separate INST + DATA bus -- or is it more like an M0??? is their benefit to placing risc-v code into a separate SRAM block -- to avoid contention *and* wait-states???

RE: executing small applications from SRAM -- performance implications

Einar Thorsrud — Mon, 16 Mar 2026 13:32:00 GMT

Hi,

The cache is 8 kB. Caching is normally quite efficient, and you will typically not see a benefit using by placing the application in RAM with caching disabled compared ro RRAM with caching enabled when caching is enabled (see current consumption for CPU running). To see the effect you can disable instruction cache using CONFIG_ICACHE=n in prj.conf or similar.

Regarding the VPR RISC-V CPU, there is only a single RRAM bank on the device, so here there will be waits of the ARM and RISC-V core attempts to access at the same time. For RAM, you can avoid it by using separate RAM banks. See Memory layout of applications using the RISC-V coprocessor of the nRF54L Series.