RE: Custom nRF52 Board Design Feedback

Yeonjun Lee — Tue, 31 Mar 2026 10:17:57 GMT

Thank you for your feedback!

I really apprciate it.

But I have few more quetion on the answer.

- This board will work within 20cm from host device. I wonder whether i need tuning or not. (But I need high transfer speed)

- Does VDD trace you mentioned that should not in layer 2 can be placed in layer 3 or bottom layer? Or can be placed through under gnd patch on layer 2,3 or bottom?

- Is this ANT line ok? Or should i organize it.

- Will i2c work on P0.03, P0.04 like this? And which i2c block should i use? i2c21, i2c22... or i2c00....etc

- Does GND fill extend to under the ANT means bottom layer? like this?

Best regards.

Yeonjun Lee

RE: Custom nRF52 Board Design Feedback

Bendik Heiskel — Tue, 31 Mar 2026 09:36:58 GMT

Hi,

The reset pin is missing the 3.9pF capacitor and the 1k resistor. These are filter components used for filtering out any RF signal coupled between the ANT pin and the reset pin.
C28 and L4 must both be moved as close to the ANT and VSS_PA pins as possible. This is how we recommend place these components:
This type of antenna needs a tuning capacitor. C30 can not be used for tuning the antenna as it is a part of the radio matching network. A capacitor should be added between C30 and the antenna feed for antenna tuning.
This trace on layer 2 can not be routed under the ANT pin.

The trace must be moved to a different layer and the GND fill extended to cover the area under the ANT pin.
The GPIO port 2 does not have a I2C peripheral. This means the SDA and SCL lines must be moved to pins on P0 or P1. The SCL signal must also be on a pin with clock support.
Please see the Pin Assignment section of the datasheet for a overview of which pins that can be used for clock signals.

Other than this the design looks OK.

Best regards,

Bendik