https://devzone.nordicsemi.com/f/nordic-q-a/128396/peripheral-access---failure-analysisHi All, In the NRF54L15 SoC, the main ARM core and the co-processor RISC core share the same set of peripherals even though both the cores can have separate sections of RAM and Flash memories. So, can the two cores have separate memory mapping for allen-USTelligent Community 13Tue, 14 Nov 2017 10:43:53 GMT