Peripheral access - failure analysis

RE: Peripheral access - failure analysis

Elfving — Fri, 12 Jun 2026 13:38:30 GMT

[quote user="raam"]then I would want the main ARM core to take over and gracefully complete (or atleast exit from) the operation.[/quote]

Interesting. I don't think there are any HW features that helps this exact use-case, but this could be communicated between the cores and we have some sw frameworks for this. The most tempting idea to me would be to use a watchdog, to make the M33 take over when the flpr runs into an issue. But I can't really imagine how moving control to the main cpu would solve this potential issue, but the possibility is there I guess. I think whether this would work would depend on the peripheral, but I have seen some examples of two cores accessing one peripheral.

[quote user="raam"]Also, another query is, if the peripherals are memory mapped, if there is any data / memory corruption in the memory map area, what is the effect on the access to the peripherals ?
[/quote]

I guess what exact effect depends on the problem. There is tamper protection and other security features on the 54L, though they might be a bit more SW-focused than something like hardware domain isolation and separate memory mapping for each core.

I think I'd answer your question better if you could be even clearer about the use-case though. I can also make the case private if you prefer. Zephyr/NCS can be a bit strict about the SW architecture setup, but it typically has features needed to address whatever you are concerned about.

Lesson 3 and 4 here might interest you, and clear things up.

Regards,

Elfving

RE: Peripheral access - failure analysis

raam — Wed, 10 Jun 2026 13:23:04 GMT

So, if we assume that I map couple of peripherals like ADC and I2C to the RISC core, and in the field, during real-time operational use case, one of the peripherals fails ( like abnormal behavior) , then I would want the main ARM core to take over and gracefully complete (or atleast exit from) the operation.Is that possible in this SoC ?

Also, another query is, if the peripherals are memory mapped, if there is any data / memory corruption in the memory map area, what is the effect on the access to the peripherals ?

Thanks Elfving for your prompt response ! Looking forward to your inputs to the above concerns...

RE: Peripheral access - failure analysis

Elfving — Wed, 10 Jun 2026 13:11:11 GMT

Hi,

That is an interesting question. I think it has the same memory mapping for the peripherals, and it is rather up to the user to make sure that there wont really be a conflict. Do you have a specific concern in mind?

Regards,

Elfving