https://devzone.nordicsemi.com/f/nordic-q-a/128483/does-the-swd-and-sck-goes-high-impedance-when-chip-is-in-reset-stateHi, I am now developing a production programmer and I want to know the behavior of SWD and SCK lines when the nRF52840 is in RESET state. Cheers, Kaushalyaen-USTelligent Community 13Wed, 17 Jun 2026 13:09:42 GMThttps://devzone.nordicsemi.com/thread/568073?ContentTypeID=1Wed, 17 Jun 2026 13:09:42 GMT137ad170-7792-4731-bb38-c0d22fbe4515:0469d223-a256-4d1e-a066-0126a994449eKazi Afroza Sultana<p>Hello,</p> <p>On the NRF52840, both SWDIO and SWDCLK are dedicated debug pin which has internal pull up and pull down resistor consequently. These are always present there as part of the dedicated SWD pin structure and remail active during reset. So, these lines are not high-impedance/floating.&nbsp;</p> <p><img style="max-height:240px;max-width:320px;" src="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/dif.hardened.svg" alt=" " /></p> <p>SWDCLK and SWDIO are the serial pins for interfacing between SW-DP and external debugger. On the ARM Cortex-M4, the debug domain is separated from the core reset domain. So, the SW_DP (SWD debug Port) stays powered and accessible even while the CPU core is held in reset via nRESET. You can read this documentation :&nbsp;<a href="https://docs.nordicsemi.com/r/bundle/ps_nrf52840/page/dif.html">Debug and trace • nRF52840 Product Specification • Technical Documentation</a></p> <p>Thanks.</p> <p>BR<br />Kazi</p> <p></p> <p><span></span></p><div style="clear:both;"></div>