https://devzone.nordicsemi.com/f/nordic-q-a/128741/coex0-load-capacitance-and-vdd-decoupling-differencesHello, I am developing a custom board using the nRF9151 and comparing the following Nordic sources: nRF9151 DK PCA10171 hardware files, version 1.0.0 / board revision 1.0.1 Current nRF9151 Product Specification Current nRF9151 Hardware Designen-USTelligent Community 13Mon, 20 Jul 2026 16:21:14 GMThttps://devzone.nordicsemi.com/thread/569258?ContentTypeID=1Mon, 20 Jul 2026 16:21:14 GMT137ad170-7792-4731-bb38-c0d22fbe4515:f1f76afc-0233-42db-ae56-58e4eb1e04d2Szabolcs<p>Hi,</p> <p>The Hardware Design Guidelines and the Reference Design in the Product Specification is always the standard that should be considered. The DK and the Thingy is for evaluation purposes, not for reference.</p> <p>Answering your questions:</p> <ol> <li>The capacitance directly on the pin should not exceed 50pF. Here, the capacitors are not connected directly to the pin, but through a 1K resistor, so it is fine. This restriction for COEX0 and COEX2 is always valid.</li> <li>This is the reference for the power supply filtering:<br /><img style="max-height:240px;max-width:320px;" src="https://devzone.nordicsemi.com/resized-image/__size/640x480/__key/communityserver-discussions-components-files/4/pastedimage1784564368262v1.png" alt=" " /><br />It is OK to use 10uF instead of the 47uF, but 47uF is the officially recommended value.</li> <li>When powered by nPM1300, VDD is usually connected to VSYS, and VDD_GPIO is connected to the digital supply (usually a buck output).</li> </ol><div style="clear:both;"></div>