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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>nRF52840: QSPI pin configuration confirmation</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/129129/nrf52840-qspi-pin-configuration-confirmation</link><description>Hi Team, 
 We are planning to use the following nRF52840 GPIOs for our current SPI interface, with the intention of migrating to QSPI in the future: 
 
 
 CSn: P0.08 
 
 
 CLK: P0.16 
 
 
 IO0 / MOSI: P0.15 
 
 
 IO1 / MISO: P1.08 
 
 
 IO2 / WPn: P0</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 09 Sep 2026 14:22:34 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/129129/nrf52840-qspi-pin-configuration-confirmation" /><item><title>RE: nRF52840: QSPI pin configuration confirmation</title><link>https://devzone.nordicsemi.com/thread/571067?ContentTypeID=1</link><pubDate>Wed, 09 Sep 2026 14:22:34 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:9494ca7f-46fa-477e-8bee-936b149b1859</guid><dc:creator>Nissanth</dc:creator><description>&lt;p&gt;Hi&amp;nbsp;Kaushik,&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Your pin selection is fine. None of the six pins you listed is restricted to &amp;quot;low frequency I/O only&amp;quot; in the pin assignment table, so all pins you mentioned can be used for standard SPI or QSPI.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Regards,&lt;/p&gt;
&lt;p&gt;Nissanth Karunanithy&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>