Clarification of GPIO configuration for SPI master

RE: Clarification of GPIO configuration for SPI master

11tacle — Tue, 16 Apr 2019 08:16:39 GMT

Hello Ole,

your valuable reply is more than three years old, though unfortunately I don't see any change in the nRF51 Series Reference Manual V3.0.1 regarding the configuration of GPIOs for usage as SPI pins. The same ambiguous information can still be found in chapter 26.1.1 imposing the SCK pin to be configured with an active input buffer...

Will there someday be a revised version of this manual ?

This very description is even also given online for the nRF52.

While I'm at it, I'd also like to propose changing the description for the SPI ENABLE register in table 227. As I am writing my own SPI driver I have to rely on good information. I had to find out the hard way that the SPI peripheral is enabled by writing a "1" to this register. As my first assumption was to set all three bits marked as "A", I never succeeded in activating SPI on my nRF51822. So please mark only bit 0 with an "A" in table 227.

BTW, in the online nRF52 Product Specification I saw that bits 0-3 are marked "A", so I am confused how to start SPI there, too, if I am ever to work with this kind of chip in the future.

2nd proposal: in the "nRF51 Series Reference Manual" please include a description of the SPI READY event register. Only the online nRF52 Product Specification offers an adequate explanation. The same holds for other event registers as well, like the TIMER Compare event registers in table 18.2.

Thank you.

RE: Clarification of GPIO configuration for SPI master

Remo — Tue, 31 May 2016 10:27:04 GMT

Thank you very much!

RE: Clarification of GPIO configuration for SPI master

Ole Bauck — Tue, 31 May 2016 09:20:53 GMT

PULL and DRIVE will still be valid for the pin configuration, so not overwritten and will always take effect.

RE: Clarification of GPIO configuration for SPI master

Artucas — Mon, 30 May 2016 16:30:26 GMT

I think so Remo, i understood it exactly like that.

RE: Clarification of GPIO configuration for SPI master

Remo — Mon, 30 May 2016 14:53:32 GMT

Thank you for the clarification!

Just to be sure, did I understand that correct that the pull-up and pull-down settings are the only GPIO settings that are not overwritten by a peripheral and therefore always take affect?

RE: Clarification of GPIO configuration for SPI master

Artucas — Mon, 30 May 2016 14:24:45 GMT

Thanks for clarifying Ole.

RE: Clarification of GPIO configuration for SPI master

Ole Bauck — Mon, 30 May 2016 14:13:48 GMT

The SPI peripheral will override the gpio pin configuration so it does not matter what it is when SPI is enabled (other than pull-up/pull-down resistors). This is a bug in the Reference Manual and has been reported internally.

RE: Clarification of GPIO configuration for SPI master

Remo — Mon, 30 May 2016 14:04:57 GMT

I know that PSELSCK, PSELMOSI, and PSELMISO are just selecting the pins, but when I enable the SPI master module I assume/expect that the SPI master takes over the control of these pins and therefore overrides the settings made in the GPIO module.

I would have expected that the suggested GPIO settings from table 221 are only relevant when the SPI master is disabled again or the chip enters the OFF mode.

RE: Clarification of GPIO configuration for SPI master

Artucas — Mon, 30 May 2016 12:50:21 GMT

Why wouldn't you? PSELSCK, PSELMOSI, and PSELMISO are only selecting which pins you are going to use for SPI. These pins do not modify the pins behavior. To modify pins behavior you have to modify it in GPIO module. It is kinda naturally . It is exactly the same in every mcu. First you select the pins used, then you modify them for desired interface.

RE: Clarification of GPIO configuration for SPI master

Remo — Mon, 30 May 2016 11:52:28 GMT

You've understood me wrong. Of course do I modify the PSELx registers, otherwise our SPI driver won't work. The question was why it is necessary to configure the SPI pins also in the GPIO peripheral module.

RE: Clarification of GPIO configuration for SPI master

Artucas — Mon, 30 May 2016 09:10:52 GMT

Well it would be good to see how "your" drivers look like, because if you don't modify values of SPI PSELSCK, PSELMOSI nad PSELMISO registers, then these registers will have default value of 0xFFFFFFFF, and that means that associated SPI master signal is not connected to any pin of your chip. So it is imposible to use SPI without modyfing these registers. Also, from reading reference manual i can see that these registers configurations are used only as long as SPI master is enabled. And i checked the manual to see about your second question, however i didn't find any answer. The only thing i was able to find is that input buffer must always be connected to the SCK pin to work.

RE: Clarification of GPIO configuration for SPI master

Remo — Mon, 30 May 2016 05:53:44 GMT

Thanks for your answer, but we aren't using the SPI library from Nordic. We use our own SPI driver.

RE: Clarification of GPIO configuration for SPI master

Artucas — Fri, 27 May 2016 22:25:21 GMT

dont know for second question, but for the first one - if you are using nordic libs for SPI, they are configuring GPIO's when creating new instance of SPI which you are using.