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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>TWI clock stretching</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/14329/twi-clock-stretching</link><description>Hello,
I am developing custom HAL driver for TWIM in NRF52 (PCA10040). The problem is that after the slave device stretches the clock signal, ninth period on SCL clock is too short (circa 1us instead of 5us).
I provide a simple code of sending function</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 01 Feb 2017 15:35:08 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/14329/twi-clock-stretching" /><item><title>RE: TWI clock stretching</title><link>https://devzone.nordicsemi.com/thread/54710?ContentTypeID=1</link><pubDate>Wed, 01 Feb 2017 15:35:08 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:a84a2faa-f942-4eda-a1b8-5ccae96701c5</guid><dc:creator>Ole Bauck</dc:creator><description>&lt;p&gt;Hi, thanks for the reminder. We are still working on figuring out this issue.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: TWI clock stretching</title><link>https://devzone.nordicsemi.com/thread/54709?ContentTypeID=1</link><pubDate>Fri, 20 Jan 2017 10:42:43 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:b268b208-9943-4a6d-b261-e261c3255057</guid><dc:creator>mjelen</dc:creator><description>&lt;p&gt;Is there any workaround? We have the same problem. Slave device pulls sometimes SCL line despite the speed reduction.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: TWI clock stretching</title><link>https://devzone.nordicsemi.com/thread/54708?ContentTypeID=1</link><pubDate>Wed, 15 Jun 2016 14:41:40 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:f3e53819-f9f5-4598-891b-2935eb7fd144</guid><dc:creator>Ole Bauck</dc:creator><description>&lt;p&gt;I can confirm that I see the same issue. Actually it seems that the pulse will be between almost zero to double of what it should be depending on how long the clock stretching last. I will discuss this internally to see if there are any workarounds. One possible workaround is to set down the speed of the master to try to avoid possible clock stretching.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: TWI clock stretching</title><link>https://devzone.nordicsemi.com/thread/54707?ContentTypeID=1</link><pubDate>Wed, 08 Jun 2016 08:37:08 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:56769284-05ee-45a6-965f-4db0120a1029</guid><dc:creator>kijemwoko</dc:creator><description>&lt;p&gt;&amp;quot;Do you mean &amp;quot;top SCL, bottom SDA&amp;quot;&amp;quot; - yes, of course. I made a mistake... I made a correction in my topic&amp;#39;s post.&lt;/p&gt;
&lt;p&gt;The problem still exists...&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: TWI clock stretching</title><link>https://devzone.nordicsemi.com/thread/54706?ContentTypeID=1</link><pubDate>Tue, 07 Jun 2016 13:08:44 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:6b79e214-1505-444e-b054-ba9285f6f5fc</guid><dc:creator>Ole Bauck</dc:creator><description>&lt;p&gt;Do you mean &amp;quot;top SCL, bottom SDA&amp;quot;, if the bottom is SCL I can&amp;#39;t see the 1us on the clock (ninth clock cycle).&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>