Does the nrf51 ADC use sample and hold?

RE: Does the nrf51 ADC use sample and hold?

Øyvind Karlsen — Thu, 16 Jun 2016 08:40:11 GMT

The bandwidth is proportional to f_SAMPLE (200 kHz), further information is limited due to intellectual property. The bandwidth and slew rate should be sufficient for you use case.

RE: Does the nrf51 ADC use sample and hold?

Nick — Thu, 16 Jun 2016 06:54:24 GMT

The 'acquisition time' section in the specs shows the source resistance (Rsource) directly in series with the acquisition capacitor. That's what made me wonder if the amplifier comes later. Are there any specs available for the dynamic performance of the amplifier (eg. bandwidth and slew rate)?

RE: Does the nrf51 ADC use sample and hold?

Øyvind Karlsen — Thu, 16 Jun 2016 06:01:12 GMT

The gain stage comes before the acquisition caps, yes.

RE: Does the nrf51 ADC use sample and hold?

Nick — Thu, 16 Jun 2016 03:38:53 GMT

The nRF52 ADC does look like it has some nice features. The configurable gain stage is something that could also be very useful for my application. I was wondering: does the gain stage come before or after the 'acquisition' capacitor?

RE: Does the nrf51 ADC use sample and hold?

Øyvind Karlsen — Wed, 15 Jun 2016 09:07:10 GMT

Is using nRF52 an option for you? The ADC samples at a much quicker rate (as low as 3 µs for low impedances).

RE: Does the nrf51 ADC use sample and hold?

Nick — Wed, 15 Jun 2016 03:39:35 GMT

After doing some investigating, unfortunately it seems that the signal does need to be stable for the entire conversion period. I'm finding that for a 10-bit conversion the signal needs to be stable for at least 68us from the time when the EVENT triggers the conversion for the result to be valid.