RE: SPI readings are shifted, inconsistent (nRF Master, FPGA Slave)

User1321 — Tue, 21 Mar 2017 17:39:54 GMT

Is there any solution to this issue that it is not just simply decreasing the SPI speed?

RE: SPI readings are shifted, inconsistent (nRF Master, FPGA Slave)

RemySphere — Fri, 08 Jul 2016 12:00:12 GMT

See here for the answer (credits to Mast)

The difference between your acquisition speed and data speed is not enough. Increasing the speed of the FPGA or decreasing the speed of the SPI does fix the alignment problem.

Your SPI clock and FPGA clock are not synchronized. This means your FPGA clock needs to run at minimum twice as fast as the SPI clock. However, since SPI is an external signal, it may not be entirely clean. There's likely jitter on your clock and/or data. A factor of 2 as difference is simply cutting it too close.

You have a factor of 3. When in doubt about the validity of your signals, keep in mind that this is close to the bare minimum. Increase the factor. As you indicated, factor 12 works. Your threshold is likely at 8 (12 / 8 = 1.5 MHz).

Also, you most probably don't need such a high speed. Data integrity is likely much more important. Build it safe first, worry about speed optimization later.

RE: SPI readings are shifted, inconsistent (nRF Master, FPGA Slave)

RemySphere — Fri, 08 Jul 2016 10:00:35 GMT

The code formatting is acting weird... don't mind the

, if I take it off it fails to format everything somehow