Issue with NRF51 unexpectedly entering debug mode

RE: Issue with NRF51 unexpectedly entering debug mode

tesc — Mon, 02 Jan 2017 10:24:23 GMT

The reference layout (PS 3.3) uses a 1k resistor.

When this is not enough, the suggested alternative is to remove the resistor and add the 1nF (or less) capacitor in its place. Note that using a capacitor instead of a resistor may affect programming speed, and for most designs using a 1k resistor solves the issue. Whether this change is needed depends on the particular PCB layout/casing/environment. See also the other suggestions in Kenneth's answer above.

RE: Issue with NRF51 unexpectedly entering debug mode

Stefan — Tue, 20 Dec 2016 13:05:50 GMT

Bumping this. We can (rarley) reproduce exact the same behaviour with 1.2mA when device is doing nothing, and 4mA when we run system_off.

The issue is triggered when you glitch the power on/off, and not even the HW reset circuit saves us since the reset is inactivated...

Is the official solution to add 1k resistor together with 1nF shunt on the SWDCLK? Since the 1k is added in PS 3.3 i assume Nordic knows that this is a problem in practice as well and should have a verified solution

RE: Issue with NRF51 unexpectedly entering debug mode

Carl — Fri, 09 Dec 2016 13:21:49 GMT

No sign of a glitch on SWDCLK. However, we have observed that placing a probe on the SWDIO/nRESET pin during power-up prevents the issue from occurring (probably due to capacitance).

RE: Issue with NRF51 unexpectedly entering debug mode

Carl — Fri, 09 Dec 2016 10:38:14 GMT

I am investigating a similar issue now. The chip appears to enter debug state (draws high currents even in system off, ignores reset pin, but otherwise behaves correctly) very rarely in cases of unusual power-on conditions. Will check for glitches on SWDCLK today. Note that the resistor on the SWDCLK line is only shown in version 3.3 of the nRF51822 PS, not version 3.1, and there is no explanatory text (which I'd expect if this is a known issue, particularly as the pin has an internal pull-down as well).

RE: Issue with NRF51 unexpectedly entering debug mode

Dave J — Thu, 13 Oct 2016 19:29:10 GMT

@Jarmo, We have not succeeded in capturing the event that is causing the NRF51 to enter debug mode. I'll keep this thread updated if we find any more information.

RE: Issue with NRF51 unexpectedly entering debug mode

Kenneth — Tue, 11 Oct 2016 12:41:21 GMT

A pull down itself doesn't provide any filtering, so if you have instant energy applied to the trace, the pull down will only reduce the time, not necessarily the level. In such case a capacitor will be a better solution. The nRF52 requires 50clock cycles + 2 x 32-bit word required to enable debug mode.

RE: Issue with NRF51 unexpectedly entering debug mode

Jarmo — Mon, 10 Oct 2016 13:01:38 GMT

My similar question is here: devzone.nordicsemi.com/.../

RE: Issue with NRF51 unexpectedly entering debug mode

Jarmo — Mon, 10 Oct 2016 12:48:56 GMT

Have you succeeded to capture such an accidental noise event in SWDCLK line? It is very hard to believe the explanation, especially when there is that 470 ohm pull-down installed. It would need really strong external field to generate enough noise into that strongly grounded line. Or at least I think so. Is the SWDCLK somehow very different compared to other GPIO pins?

Yes, we are experiencing the same problem and it is really very frustrating. Is the nRF52832 any better in this sense?

RE: Issue with NRF51 unexpectedly entering debug mode

Kenneth — Wed, 21 Sep 2016 19:35:25 GMT

Hi,

The short answers to your questions are: Yes, Yes, and No.

Debug interface mode is initiated by clocking one clock cycle on SWDCLK with SWDIO=1 [See ch. 11.1.2 Debug interface mode in nRF51 Reference Manual v3.0].

Depending on layout, grounding and housing, it is not unlikely that the SWDCLK trace can act as an "antenna" and for instance, if the device is subjected to strong electromagnetic fields close by (for example a cell phone at high output power), this might be picked up.

For the majority of the applications I am aware of this is not a problem, and this is typically something developers experience during prototype stage when the bare PCB is exposed to the environment.

We recommend to add a small resistor on the SWDCLK line to make it more robust [See reference circuitry in nRF51822 Product specification v3.1]. The resistor should be as small as possible, yet still make it possible to program the chip. We have recommended 1kohm.

If you still experience that the product enter debug mode, you might consider additional steps. For instance make the SWDCLK track as short as possible, have ground on all sides of the track to avoid crosstalk with other digital lines, and avoid that it can act as an antenna. You might consider replace the 1kohm with a 1nF capacitor (or less), this might affect programming speed.

As a last resort you might even consider connect a spare GPIO on the nRF51822 directly to SWDCLK, and set the spare GPIO to output low after power up. This will prevent re-programming, so you might want to have some means for the application to release the pin.

RE: Issue with NRF51 unexpectedly entering debug mode

Roger Clark — Mon, 19 Sep 2016 23:43:48 GMT

I'm not sure if this is related.

But I posted a question where the nRF51 would not enter debug.

I have it connected, all the time via JLink, and I uploaded some code, but I think I must have had a pointer overflow. But when I tried to upload, JLink would not connect.

I had to power cycle the device (a Smart Watch) in order to be able to upload.

PS. As far as I'm aware, no one answered my question about not being able to enter debug.