nRF52832: UART buffers, PHY interface questions

RE: nRF52832: UART buffers, PHY interface questions

joedamato — Thu, 29 Sep 2016 06:24:59 GMT

Thanks a lot RK. You answered my question and beyond :)

RE: nRF52832: UART buffers, PHY interface questions

RK — Thu, 29 Sep 2016 06:21:25 GMT

Haven't come across any - the closest in my mind is the built-in PCIe on the Intel chips which is blisteringly fast and is so native it's almost part of the bus. Then there's varying types of external memory, from DRAM, which is on the bus to some of the chips which have a simple parallel peripheral you can use a few pins to interface to . Beyond those and the ability of two processors from the same family to work together, not really.

RE: nRF52832: UART buffers, PHY interface questions

joedamato — Thu, 29 Sep 2016 06:16:19 GMT

RK, thanks for your inputs. You are right I will use SPI. One side question though: are there some wifi chips that expose their buses? Or is it just a Ethernet thing?

RE: nRF52832: UART buffers, PHY interface questions

RK — Thu, 29 Sep 2016 06:13:26 GMT

no you can't connect anything direct to the CPU, the buses are not exposed, there is no peripheral which is external memory mapped. And I'm not sure I'd call 4MHz SPI a slow protocol, that's 4x the underlying bit rate of BLE, which has an effective bit rate lower than that anyway.

Data rate's not your problem, if you have a problem at all it's available RAM for buffering the data you want to stream on and off. And if that is a real issue for you, you're using the wrong chip.

RE: nRF52832: UART buffers, PHY interface questions

joedamato — Thu, 29 Sep 2016 05:38:10 GMT

My goal was to avoid those slow protocols by directly connecting the chip MAC with the CPU MAC interface (Cortex A53 support that). That would make this solution native BLE and potentially faster by reading bounds directly and accessing buffers in a very fast fashion.

RE: nRF52832: UART buffers, PHY interface questions

RK — Thu, 29 Sep 2016 00:22:45 GMT

With EasyDMA list mode the buffers are pretty much as big as you want them to be, subject to available RAM.
I don't understand this question at all. You use PHYs when you interface MACs to different physical transport mediums, here you are connecting two chips with traces.

I wouldn't use UART for this myself unless I had to, I'd use SPI, which you can run up to 4MHz. Also since the master controls the clock, it can clock in data whenever it wants, you just have to keep the buffers on the nRF full.