64-bit floating point

RE: 64-bit floating point

paul_tanner — Sat, 26 Aug 2017 13:17:14 GMT

Thx Hakon, that does fix the issue. I tried both sprintf and SEGGER_RTT_printf. The latter did not work so I use sprintf and feed the output of that to the RTT call so all is good.

RE: 64-bit floating point

Håkon Alseth — Fri, 25 Aug 2017 05:42:24 GMT

Could you try adding "LDFLAGS += -u _printf_float", then see if it prints float's correctly?

Cheers, Håkon

RE: 64-bit floating point

paul_tanner — Thu, 24 Aug 2017 16:17:29 GMT

I'm trying to use printfs with floats on nRF52 with SDK 12.2 using armgcc I just get spaces printed. My Makefile contains:

LDFLAGS += -mthumb -mabi=aapcs -L $(TEMPLATE_PATH) -T$(LINKER_SCRIPT)
LDFLAGS += -mcpu=cortex-m4
LDFLAGS += -mfloat-abi=hard -mfpu=fpv4-sp-d16
# let linker to dump unused sections
LDFLAGS += -Wl,--gc-sections
# use newlib in nano version
LDFLAGS += --specs=nano.specs -lc -lnosys

(as above). What else do I need to check?

RE: 64-bit floating point

Håkon Alseth — Tue, 08 Nov 2016 10:56:03 GMT

Hi,

The difference between doing float manipulation with and without FPU enabled is quite huge. I did a test with CMSIS-DPS fft example (\CMSIS\DSP_Lib\Examples\arm_fft_bin_example\ARM) a while back, and the difference is huge. Also note that there's a fft example now in SDK v12 (I have not benchmarked that one).

Compiled in Keil, all with -O3 optimization.

nRF51x22 : 198 ms 
nRF52832 w/o FPU :40.8 ms 
nRF52832 w/FPU : 2.84 ms

You will definitely benefit from tuning on the FPU if you're doing double/float operations.

To answer your questions:

Besides power/speed when performing a single-precision operation, no change.
most examples have FPU enabled by default on the nRF52832. In keil, you set this in your project settings under "Target -> Floating point hardware" drop-down menu. Similar setting in IAR settings (Under the Target section). With GCC, the FPU is set under CFLAGS and LDFLAGS with "-mfloat-abi=hard -mfpu=fpv4-sp-d16"
The FPU in the nRF52 is a component that is "included" in the ARM M4F core that we have licensed from ARM. According to ARM, it is not fully compliant with IEEE 754 (only for Single Precision): infocenter.arm.com/.../index.jsp infocenter.arm.com/.../index.jsp

The FPU provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. The FPU contains 32 single-precision extension registers, which you can also access as 16 doubleword registers for load, store, and move operations.

edit: Oh, almost forgot. a 64-bit float is a "double", and is of type "float64_t" (which is just typedef'ed from a double).

Cheers, Håkon