nRF52832 MPU TEX,S,B,C bits setup

RE: nRF52832 MPU TEX,S,B,C bits setup

tkorsdal — Thu, 10 Nov 2016 09:16:09 GMT

The problem was incorrect setting of the size field.

For TEX,S,B and C bits I went with the suggestions in section B3.1 of the ARMv7-M architecture reference manual:

Code regions as WT (Write through) (TEX,S,B,C)=(110,1,1,0) RAM Data regions as WBWA (Write-back, write-allocate). (TEX,S,B,C)=(101,1,0,1)

RE: nRF52832 MPU TEX,S,B,C bits setup

tkorsdal — Thu, 10 Nov 2016 09:06:30 GMT

@Hung Bui: Thank you. I have been studying the ARMv7-M-arm for MPU settings. How to set up cache for particular device is not described, and I could not find this information in the nRF52 documentation either. But the problem was elsewhere and I solved it. I will post the answer here and how my MPU settings ended up.

RE: nRF52832 MPU TEX,S,B,C bits setup

Hung Bui — Thu, 10 Nov 2016 08:41:16 GMT

@tkorsdal: I'm afraid that we don't have any example for the Cortex M4 MPU. The best source for explanation of the register should be from the "ARMv7-M Architecture Reference Manual" at section B3.5.9

What exactly you want to do with the memory protection ? Would the BPROT and the MWU on the nRF52 can do the job ?