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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>can nrf51822 master SPI clock use 8M?</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/17922/can-nrf51822-master-spi-clock-use-8m</link><description>we follow the nRF51_Series_Reference_manual v3.0, set the master SPI clock to 8M. but found when in mode 0, the MOSI change near at SCLK rise edge, not in fall edge.
our hardware engineer found this: the master SPI clock be 4M in section 8.9 in nRF51822_PS</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 23 Nov 2016 08:37:50 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/17922/can-nrf51822-master-spi-clock-use-8m" /><item><title>RE: can nrf51822 master SPI clock use 8M?</title><link>https://devzone.nordicsemi.com/thread/69097?ContentTypeID=1</link><pubDate>Wed, 23 Nov 2016 08:37:50 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ba7fbc67-e7c8-4138-ad82-9fdd21f96038</guid><dc:creator>Petter Myhre</dc:creator><description>&lt;p&gt;I think &lt;a href="https://devzone.nordicsemi.com/question/2990/spi-master-speed-of-nrf51822/"&gt;this&lt;/a&gt; answers your question.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>