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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Errata 138 - Spurious emission on GPIO exceeds limits in radiated tests</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/18476/errata-138---spurious-emission-on-gpio-exceeds-limits-in-radiated-tests</link><description>Hi,
I&amp;#39;m not sure if I understand the new reference layout correctly. There are new NP0 12pF capacitors on pin 25 and pin 26 to suppress the spurious emission, but are they always needed or only if these pins are connected to a trace? According to the</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 19 Dec 2016 13:55:06 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/18476/errata-138---spurious-emission-on-gpio-exceeds-limits-in-radiated-tests" /><item><title>RE: Errata 138 - Spurious emission on GPIO exceeds limits in radiated tests</title><link>https://devzone.nordicsemi.com/thread/71276?ContentTypeID=1</link><pubDate>Mon, 19 Dec 2016 13:55:06 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:48856978-8ed8-4445-b8bb-0678d838a2f1</guid><dc:creator>Hung Bui</dc:creator><description>&lt;p&gt;Hi Moritz,&lt;/p&gt;
&lt;p&gt;If you don&amp;#39;t plan to use pin P0.25 and P0.26 you don&amp;#39;t have to use the 12pF, and simply connect the pins to center pad.&lt;/p&gt;
&lt;p&gt;I don&amp;#39;t have more information about the affected frequencies.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>