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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Minimum clock speed for SWD?</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/18558/minimum-clock-speed-for-swd</link><description>We&amp;#39;re trying to bit-bang SWD to program an nRF52832, and we&amp;#39;re running into some problems getting the nRF52 to respond. One theory is we&amp;#39;re not generating a high enough clock speed. Right now we&amp;#39;re using a 10khz clock. 
 What&amp;#39;s the minimum clock speed</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Sun, 13 Aug 2017 11:01:24 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/18558/minimum-clock-speed-for-swd" /><item><title>RE: Minimum clock speed for SWD?</title><link>https://devzone.nordicsemi.com/thread/71620?ContentTypeID=1</link><pubDate>Sun, 13 Aug 2017 11:01:24 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:e8e56e4c-377c-4229-a318-7d142b01b5b7</guid><dc:creator>Roger Clark</dc:creator><description>&lt;p&gt;@curtisHx&lt;/p&gt;
&lt;p&gt;What processor are you using to bit-bang the SWD.&lt;/p&gt;
&lt;p&gt;Only managing 10khz is quite slow for modern processors.&lt;/p&gt;
&lt;p&gt;I know bit-banged I2C on a 72Mhz STM32F103 can be made to run at 400kHz without too many optimisations.&lt;/p&gt;
&lt;p&gt;Are you running on an old slow processor ??&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Minimum clock speed for SWD?</title><link>https://devzone.nordicsemi.com/thread/71623?ContentTypeID=1</link><pubDate>Sun, 13 Aug 2017 07:48:07 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:f80eeb0c-3418-4668-8ea6-66a905e31881</guid><dc:creator>slowcoder</dc:creator><description>&lt;p&gt;I guess that depends on what state SWCLK/SWDIO is in when it stops, and for how long a &amp;quot;moment&amp;quot; is. If both lines are low for 100uS or longer (not &lt;em&gt;entirely&lt;/em&gt; sure about this value), I guess the nRF51 could interpret it as a reset due to the shared SWDIO/nRESET functionality.&lt;/p&gt;
&lt;p&gt;However, if you&amp;#39;re just talking about very minor changes in timing, it seems to handle that well. Every now and then the MCU that I&amp;#39;m implementing this on wants to service an IRQ or something else, and I get a SWCLK that&amp;#39;s about twice as long. The nRF51 seems to handle this just fine.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Minimum clock speed for SWD?</title><link>https://devzone.nordicsemi.com/thread/71621?ContentTypeID=1</link><pubDate>Sat, 12 Aug 2017 10:12:39 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:2972f753-f11b-4e6b-80ff-4827e6b1c5a4</guid><dc:creator>slowcoder</dc:creator><description>&lt;p&gt;In case anyone else plays around with very slow SWD (and, as this is the only relevant discussion on the internet about the &lt;em&gt;slowest&lt;/em&gt; SWD speed), I just discovered that the nRF51 does indeed &lt;em&gt;not&lt;/em&gt; ACK (or, clock out &lt;em&gt;anything&lt;/em&gt;) if you&amp;#39;re running at 18KHz. After clocking up to 190KHz (no other changes), the nRF51 started to respond.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Minimum clock speed for SWD?</title><link>https://devzone.nordicsemi.com/thread/71619?ContentTypeID=1</link><pubDate>Fri, 23 Dec 2016 14:16:46 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:38805ab8-05f7-408c-93ff-73a99abcd782</guid><dc:creator>CurtisHx</dc:creator><description>&lt;p&gt;Thanks for checking that out.  Turns out the code wasn&amp;#39;t correctly calculating the parity bit, and the nRF52 wasn&amp;#39;t acking per the SWD spec.  So it looks like we can use our 10khz clock, just with the understanding that we&amp;#39;re outside of the spec and things may not work correctly.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Minimum clock speed for SWD?</title><link>https://devzone.nordicsemi.com/thread/71618?ContentTypeID=1</link><pubDate>Fri, 23 Dec 2016 07:51:52 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:9e9315fc-7aca-42b2-a29e-028b51d8346c</guid><dc:creator>Susheel Nuguru</dc:creator><description>&lt;p&gt;I see that this information seems to be missing in the nRF52 manuals. I would assume that it should be the same requirement as for nRF51 which was a minimum of 125 KHz mentioned &lt;a href="http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf#page=40"&gt;here&lt;/a&gt;. 10 KHz that you have on your system seems too less.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>