GPIO state unpredictable when Vdd is below 1.6V URGENT!!!

RE: GPIO state unpredictable when Vdd is below 1.6V URGENT!!!

TY — Tue, 14 Feb 2017 07:13:28 GMT

Why a diode? Do you think the threshold voltage would avoid the Darlington Array to turn on?

RE: GPIO state unpredictable when Vdd is below 1.6V URGENT!!!

Roger Clark — Mon, 13 Feb 2017 22:49:15 GMT

Have you considered putting a diode between the GPIO and the Darlington input?

RE: GPIO state unpredictable when Vdd is below 1.6V URGENT!!!

Daniel Wang — Mon, 13 Feb 2017 19:49:12 GMT

Default pin state is: Input pin, No Pull, Disconnected input buffer, S0S1 drive, Sense Disabled

RE: GPIO state unpredictable when Vdd is below 1.6V URGENT!!!

Krunal Desai — Mon, 13 Feb 2017 19:01:12 GMT

Isn't <1.7V undefined operating region for the part? I'd argue that this is exactly what pull-down resistors are for -- enforcing the state of the system before a device comes out of reset / can assert pin states. The internal GPIO cells may simply not function below a certain VDD where the transistor Vt can't be met.

10K-100K PDs would fix this I think -- 330uA "wasted" with a 10K, 33 with a 100K assuming 3.3V target VDD. But I would treat those pins as 100% floating nets until the nRF can operate and set output levels.

An alternate would be finding a part with an EN pin or similar, where you can pay the penalty for a pull-down only once instead of per channel.