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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>nRF24L01+ raises IRQ on PRX side only once</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/1983/nrf24l01-raises-irq-on-prx-side-only-once</link><description>Hello, 
 I am frustrated by a pair of nRF24L01+ communicating with each other, where all the Enhanced ShockBurst features are enabled. 
 The PRX is initialised as follows: 
 ****** nRF24L01+ register set ******
Register 0x00	=	0x0F
Register 0x01</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Sun, 28 Dec 2014 17:21:35 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/1983/nrf24l01-raises-irq-on-prx-side-only-once" /><item><title>RE: nRF24L01+ raises IRQ on PRX side only once</title><link>https://devzone.nordicsemi.com/thread/8505?ContentTypeID=1</link><pubDate>Sun, 28 Dec 2014 17:21:35 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:8aadd63c-2650-4547-8b68-f10ebb2d13a5</guid><dc:creator>Ralph Kr&amp;#252;ger</dc:creator><description>&lt;p&gt;I&amp;#39;m not absolutely sure (because there MAY be other changes done during a somewhat longer development cycle), but most probably this solved the problem. Strange though, since this is not what someone would expect after having read the manual.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF24L01+ raises IRQ on PRX side only once</title><link>https://devzone.nordicsemi.com/thread/8506?ContentTypeID=1</link><pubDate>Fri, 21 Nov 2014 09:36:57 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:657a79d9-ff30-4d02-b569-8ab45efe0c35</guid><dc:creator>Derek Goslin</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;I have experienced the same issue possibly caused for the same reason hopefully this can save someone else time and sanity.&lt;/p&gt;
&lt;p&gt;I paired the problem back to a simple test case.&lt;/p&gt;
&lt;p&gt;Configure the TX and the RX with all default initialized values, i.e. PWR_UP = 1 and set CE = 1 and PRIM_RX = 0 on TX. Optionally you can enable Dynamic Payload Length and W_TX_PAYLOAD_NOACK command.&lt;/p&gt;
&lt;p&gt;When the TX sends a packet with or without ACK the RX will see the initial RX_DR interrupt.&lt;/p&gt;
&lt;p&gt;In my interrupt handler I was first reading and &amp;quot;clearing&amp;quot; via write of a 1 to the STATUS register bits&lt;/p&gt;
&lt;pre&gt;&lt;code&gt;uint8_t hal_nrf_get_clear_irq_flags(void)
{
  return hal_nrf_write_reg(STATUS, (BIT_6|BIT_5|BIT_4)) &amp;amp; (BIT_6|BIT_5|BIT_4);
}
&lt;/code&gt;&lt;/pre&gt;
&lt;p&gt;Then I was using the return value to determine the source of the interrupt. And handling it as follows:&lt;/p&gt;
&lt;pre&gt;&lt;code&gt;while (!hal_nrf_rx_fifo_empty())
{
	hal_nrf_read_rx_pload(pload);
}

radio_set_status (RF_RX_DR);
&lt;/code&gt;&lt;/pre&gt;
&lt;p&gt;The handler reads the payload into a buffer called pload and then sets a status flag when not more packets are in the RX fifo.&lt;/p&gt;
&lt;p&gt;NOTE: The astute will notice that this code can cause dropped packets. For the packet rate that I am using this is adequate. For higher speed rates this code fails.&lt;/p&gt;
&lt;p&gt;My MCU is basically in a sleep state awaiting an external interrupt. The interrupt from the NRF24L01P device wakes the MCU up and execution continues. In the MCUs code path post wake up I was doing the following:&lt;/p&gt;
&lt;pre&gt;&lt;code&gt;radio_status_t status = radio_get_status();
			
if(status == RF_RX_DR)
{
	uint16_t packet_info = hal_nrf_read_rx_pload((uint8_t *) &amp;amp;packet);
&lt;/code&gt;&lt;/pre&gt;
&lt;p&gt;The hal_nrf_read_rx_pload methods is defined as the following:&lt;/p&gt;
&lt;pre&gt;&lt;code&gt;uint16_t hal_nrf_read_rx_pload(uint8_t *rx_pload)
{
  return hal_nrf_read_multibyte_reg(UINT8(HAL_NRF_RX_PLOAD), rx_pload);
}
&lt;/code&gt;&lt;/pre&gt;
&lt;p&gt;The hal_nrf_read_multibyte_reg method executes the R_RX_PL_WID command to get the payload length and then reads the payload via the R_RX_PAYLOAD command.&lt;/p&gt;
&lt;p&gt;It is this sequence of reads that seems to put the NRF24L01P into a strange state whereby the TX gets an ACK but no interrupt occurs.&lt;/p&gt;
&lt;p&gt;Another behavior that I observed was that the TX will get an ACK for the first three packets and then transmission fails due to MAX_RT. This makes sense in light of the above as the RX is not clearing its FIFO because there are not interrupts being fired to the MCU to read the packet data.&lt;/p&gt;
&lt;p&gt;To resolve the problem I simply stopped reading from the receive payload registers, which was the source of this bug, and read from the payload buffer instead. Alternately I could have modified the interrupt code to simply set the status and allowed the MCU main like code to read the receive registers.&lt;/p&gt;
&lt;p&gt;Regards Derek&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF24L01+ raises IRQ on PRX side only once</title><link>https://devzone.nordicsemi.com/thread/8504?ContentTypeID=1</link><pubDate>Wed, 26 Mar 2014 11:20:21 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ac213eb1-41eb-469e-9a39-7c93140d6a2b</guid><dc:creator>H&amp;#229;kon Alseth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;You should enable the PIPEs that you&amp;#39;re using in registers RX_PW_Px on both sides.
If these are set to &amp;#39;0&amp;#39; the pipe is not used.
For the PTX it&amp;#39;s usually only RX_PW_P0.&lt;/p&gt;
&lt;p&gt;Best regards
Håkon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF24L01+ raises IRQ on PRX side only once</title><link>https://devzone.nordicsemi.com/thread/8503?ContentTypeID=1</link><pubDate>Tue, 25 Mar 2014 15:57:14 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:437e9f1f-56dc-40df-9fdf-899eb27acc62</guid><dc:creator>Ralph Kr&amp;#252;ger</dc:creator><description>&lt;p&gt;Yes Håkon, both conditions/procedures you named are fulfilled.&lt;/p&gt;
&lt;p&gt;What amazes me is the fact, that exactely this kind of communication already worked in another project (based on another architecture).&lt;/p&gt;
&lt;p&gt;And, as far as I can see, the inner state of the nRF24L01+ (i.e. its register contents) as well as its outer state (signal lines, namely CE) are identical when receiving the first message from the PTX and any following message. But nevertheless, there MUST be a difference anywhere...&lt;/p&gt;
&lt;p&gt;I am totally clueless :/&lt;/p&gt;
&lt;p&gt;Any further guesses/hints?&lt;/p&gt;
&lt;p&gt;Best regards
Ralph&lt;/p&gt;
&lt;p&gt;In case you want to check for yourself:&lt;/p&gt;
&lt;p&gt;The PTX registers are:&lt;/p&gt;
&lt;p&gt;****** nRF24L01+ register set ******
Register 0x00	=	0x0E
Register 0x01	=	0x3F
Register 0x02	=	0x01
Register 0x03	=	0x01
Register 0x04	=	0x2F
Register 0x05	=	0x00
Register 0x06	=	0x26
Register 0x07	=	0x0E
Register 0x08	=	0x00
Register 0x09	=	0x00
Register 0x0A	=	0x01,	0x01,	0x42,	0xE7,	0xE7
Register 0x0B	=	0xFF,	0xFF,	0x42,	0xC2,	0xC2
Register 0x0C	=	0xFF
Register 0x0D	=	0xFF
Register 0x0E	=	0xFF
Register 0x0F	=	0xFF
Register 0x10	=	0x01,	0x01,	0x42,	0xE7,	0xE7
Register 0x11	=	0x00
Register 0x12	=	0x00
Register 0x13	=	0x00
Register 0x14	=	0x00
Register 0x15	=	0x00
Register 0x16	=	0x00
Register 0x17	=	0x11
Register 0x1C	=	0x3F
Register 0x1D	=	0x07&lt;/p&gt;
&lt;p&gt;I use only 3 address bytes, so (0x01, 0x01, 0x42) is the relevant part.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF24L01+ raises IRQ on PRX side only once</title><link>https://devzone.nordicsemi.com/thread/8502?ContentTypeID=1</link><pubDate>Tue, 25 Mar 2014 13:57:50 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ddf718df-56f3-4845-81c5-aa1148814c47</guid><dc:creator>H&amp;#229;kon Alseth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;On the PTX side, are you setting &amp;quot;TX_ADDR&amp;quot; register equal to &amp;quot;RX_PW_P0&amp;quot;? If not, the auto-acking will not work properly.&lt;/li&gt;
&lt;li&gt;How are you clearing the STATUS (0x07) register?
You should read the content, then write &amp;#39;1&amp;#39; to the bits to clear it;
statusval = read_reg(STATUS);
retval = write_reg(STATUS, statusval);&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;Best regards
Håkon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>