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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>GPIO state during deepest sleep mode</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/19942/gpio-state-during-deepest-sleep-mode</link><description>Hi,
Do the nRF52 GPIOs retain their pullup/down or drive characteristics when in its deepest sleep mode? VCC is still applied, but otherwise, the chip is to consume a minimum of power, waiting for a wakeup on another GPIO.
The question is what happens</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Thu, 23 Feb 2017 11:42:34 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/19942/gpio-state-during-deepest-sleep-mode" /><item><title>RE: GPIO state during deepest sleep mode</title><link>https://devzone.nordicsemi.com/thread/77609?ContentTypeID=1</link><pubDate>Thu, 23 Feb 2017 11:42:34 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:3a792ade-039e-4c66-ab8d-b0bc5c3302aa</guid><dc:creator>PM</dc:creator><description>&lt;p&gt;Thank you.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: GPIO state during deepest sleep mode</title><link>https://devzone.nordicsemi.com/thread/77608?ContentTypeID=1</link><pubDate>Thu, 23 Feb 2017 09:00:23 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:5c1ea7ba-39c6-4cbc-8615-a9fd83747bf6</guid><dc:creator>Sigurd</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;The GPIO configuration is retained in System OFF mode, and the GPIO will keep its state in System OFF mode.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>