Power Consumption in Deep Sleep Mode without Pin Reset

RE: Power Consumption in Deep Sleep Mode without Pin Reset

Stian Røed Hafskjold — Thu, 16 Mar 2017 09:26:02 GMT

You should add a 1kOhm pull-down to the SWDCLK line to prevent it from accidentally entering debug mode. It turns out the internal pull-down is not strong enough in some situations. Please see the reference schematic: infocenter.nordicsemi.com/.../ref_layout.html

RE: Power Consumption in Deep Sleep Mode without Pin Reset

Nobody13 — Wed, 15 Mar 2017 08:39:38 GMT

I think so. I used a LED as indicating label if chip is in system on or in system off state. After switching off, LED is off.

After serveral tests it seems that debug mode is sometimes accidentally entered. Despited pin reset. 19 of 20 switch off works, one not.

The SWDCLK pin seems to be in a floating state, causing the chip sometimes to start in debug mode. I think I try a pulldown resistor of 1kOhm on the SWDCLK. Despite documentation...

RE: Power Consumption in Deep Sleep Mode without Pin Reset

endnode — Tue, 14 Mar 2017 20:11:02 GMT

Hi Nobody,

I would have the same question as Dave: how do you know that chip really entered SYSTEM OFF ("deep sleep" is confusing, there is nothing called like that on nRF5x;)? Do you have e.g. some GPIO or UART debug line which clearly shows that chip never returns from particular call (if you use Soft Device then you either need to disable it first or use sd_power_system_off call) and similar at system start up to show that it was in SYSTEM OFF until it got GPIOTE wake-up?

Cheers Jan

RE: Power Consumption in Deep Sleep Mode without Pin Reset

Dave_couling — Tue, 14 Mar 2017 18:00:47 GMT

Likely this is the chip in Debug mode. After a pin reset or power reset it exits from this mode and returns to normal power conusmption.