Timer Drift Clarification

RE: Timer Drift Clarification

Sigurd — Wed, 10 May 2017 13:38:43 GMT

Hi again,

You should set the NRF_CLOCK_LF_XTAL_ACCURACY_XX_PPM to match the PPM of the crystal you are using. The SoftDevice uses this information in calculating how long the BLE TX/RX windows should be. In order to measure the drift you should do this 100% in hardware (using ppi/gpiote to toggle a GPIO) and with a oscilloscope.

RE: Timer Drift Clarification

jpelo — Tue, 28 Mar 2017 15:59:27 GMT

thank you for the followup. i'm using external xtals for both. one thing i did notice when checking this is i'm setting the accuracy to NRF_CLOCK_LF_XTAL_ACCURACY_50_PPM when i init/enable softdevice which could explain the additional drift -> need to source why this was set loose (since this tolerance covers a temp range for the xtal beyond what we need/expect). the information on how this is used to calculate the timing windows is very sparse (in terms of determining how this adds) - have you seen a good explanation of how this is used? in terms of the code snippet, its not easily postable -> sampling at 100hz and adding a timestamp from rtc to sample data on sample - i get in/out of int handler in plenty of time and i could expect some jiggle of the timestamp but in trends repeatable at ~1ms/11s.

RE: Timer Drift Clarification

Sigurd — Tue, 28 Mar 2017 11:49:06 GMT

Since you are in practice measuring the relative drift between the two crystals, a worst-case scenario is that 32K is at +20ppm, 32M is at -40ppm, so you get 60 ppm drift, but 90ppm seems high. Are you sure that HFCLK(TIMER) uses the external 32MhHz crystal, and that the LFCLK(RTC) uses the 32k external crystal? Check the CLOCK register, LFCLKSTAT SRC and HFCLKSTAT SRC. If both are correct, could you post the code that you use to measure the drift ?

RE: Timer Drift Clarification

jpelo — Tue, 28 Mar 2017 06:23:26 GMT

thanks for the response Sigurd. yeah, i'm calculating the same (~90ppm) which is why i asked the question. i'm measuring my drift based on rtc ticks vs us timer ticks (time stamp from rtc). 32k is 20ppm. unfortunately im using a module so dont have direct access to the 32M inside, but assume its 40ppm or less. considering the latency of up to 1/16M and the 2 xtal tolerances, in absence of error this is possible?

RE: Timer Drift Clarification

Sigurd — Mon, 27 Mar 2017 07:37:01 GMT

So with a 1ms drift every 11s, that’s about ~90 ppm frequency drift. Yes, Shorts should not require CPU activity. External crystals have often have similar PPM, and are therefore not calibrated against each other. The internal RC oscillator on the other hand is normally calibrated against the HFCLCK.

What PPM do you have on your crystals? How do you measure the drift?