I2S timing

RE: I2S timing

Jørn — Tue, 25 Apr 2017 15:11:56 GMT

According to the GPIO chapter of the nRF52832 the rise and fall times of the GPIO with high drive are 4-8 ns with capacitive loads between 15-50 Pf.

According to page 9 (chapter 7.7) of the TAS5760L datasheet setup and hold time needs to be a minimum of 8-12 ns for the above mentioned rise and fall times. Maximum rise and fall times are set to 8 ns.

Page 460 of the nRF52832 datasheet specifies setup times as minimum 20ns, and hold times as 15 ns.

I therefore do believe that with high drive the timings should be within the specifications of the TAS5760L, as long as the input capacitances lie in the range of 15-50 pF.

RE: I2S timing

Erblin — Tue, 25 Apr 2017 14:48:28 GMT

The TWI pins are the default arduino TWI pins (P27&P26), while the I2S uses 3, 4, 28 and 29. So pins 26 to 29 are positioned relatively closed to each other. I can just exchange 3 and 4 with 27 and 26 to make them further apart. The TWI was set to 400 KHz, there is no problem for changing it to 100 KHz if necessary.

But is the GPIO's rise time within specification when increasing the pins drive strength?

RE: I2S timing

Jørn — Tue, 25 Apr 2017 09:35:03 GMT

You're right that the rise and fall timing requirements do look out of spec when comparing them to the GPIO electrical specification of the nRF52832, and high drive mode will probably be necessary. Your drive initialization looks correct.

How are your I2S pins positioned relative to your TWI pins, and what's your TWI clockrate? If you are using the internal pull-ups the TWI port can be a bit sensitive to noise, and I suspect the higher current drain of the I2S might be interfering with it. You could try to either change output pins so they are further apart, or add a smaller external pull-up to the TWI, rather than the internal one, to reduce its sensitivity to noise.

RE: I2S timing

Erblin — Thu, 20 Apr 2017 19:37:50 GMT

Hi,

yes I have seen this post before and I have tried the solutions he suggested, but it wasn't working. I have used the DAC in both hardware & software(i2c) control mode, but both solutions didn't work.

But I am starting to wonder if these specifications(chapter 7.7link to datasheet) of the serial audio port in the DAC may not be met from the nRF52832. I still haven't found any information in the infocenter in order to check if it is within the specs.

I have tried changing the drive strength of the I2S pins, but I am unsure if i did it correctly, here is what I did after configuring the I2S:

NRF_GPIO->PIN_CNF[MCK_SCK_PIN] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos);  
			NRF_GPIO->PIN_CNF[LRCK_PIN] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos);  
			NRF_GPIO->PIN_CNF[BCK_PIN] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos);  
			NRF_GPIO->PIN_CNF[SDOUT_PIN] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos);

Doing this made the I2C/TWI unstable and the DAC didn't acknowledge any of the transfers.

-Erblin

RE: I2S timing

Jørn — Thu, 20 Apr 2017 12:37:38 GMT

Hello Erblin

With the settings you mention in your post at Texas Instruments you should have a LRCLK, and SCLK error of approximately 3.1% which is within the 10% specified in the I2S Specification.

Both of these are also within the 4% Alex Bhandari-Young at TI's forum had found for a similar product.

In the TAS5760L product specification, legal clock ratios for SCLK/LRCLK are 32, 48 and 64. With your settings, this ratio is 32. Legal clock ratios for MCLK/LRCLK is 64, 128, 192, 256, 384 and 512. With your settings, this ratio is 64.

As of yet I have not found any specific reason the nRF52832 should not be compatible with the TAS5760L, as all values seem to meet the requirements. I see Alex Bhandari-Young with TI has requested more information on clock tolerances, it will be interesting to see what he finds.

I have found a post on Texas Instruments' support forum, which seems similar to your issue e2e.ti.com/.../1797838 Please have a look and see if that can be of help.

Best regards

Jørn Frøysa