CPU halt during flash erase

RE: CPU halt during flash erase

Susheel Nuguru — Wed, 26 Apr 2017 11:53:35 GMT

EasyDMA once started will not be affected by CPU halt.

RE: CPU halt during flash erase

telemedcar — Wed, 26 Apr 2017 10:49:24 GMT

Does CPU hold have any impact on SAADC and EasyDMA ? Or can I safely assume that all ADC samples can be stored in SRAM during CPU hold ?

RE: CPU halt during flash erase

Susheel Nuguru — Thu, 20 Apr 2017 10:15:27 GMT

not sure what you mean here. PPI can only be used to communicate between two peripherals within the nRF chip. You could probably do a PPI->Timer counter increment task connection to count how many events happened when the CPU is halted. But this method is very tricky to implement because you should find a way to enable this setup just before CPU is halted and disable it immediately when CPU wakes up else you will get false number in the Timer counter. What is your use case?

RE: CPU halt during flash erase

telemedcar — Thu, 20 Apr 2017 06:26:55 GMT

can using PPI help to prevent the case that signal transitions can be lost when CPU is halted ?

RE: CPU halt during flash erase

Susheel Nuguru — Wed, 19 Apr 2017 14:14:25 GMT

flash erase can take long time, if there are more than one interrupt from the same source, then it will be only pended once to ARM NVIC as pending is single buffered. So yes , they can be lost.

RE: CPU halt during flash erase

telemedcar — Wed, 19 Apr 2017 12:43:37 GMT

Thanks. Do I/O hardware interrupts get lost during the time when CPU is halted due to flash erase ?

RE: CPU halt during flash erase

Susheel Nuguru — Wed, 19 Apr 2017 12:40:55 GMT

When you are using fstorage, then it uses a separate timeslot assigned from the BLE softdevice which is BLE friendly to do the flash operation. In simple terms, fstorage calls have lower priority than the BLE activity and hence cannot break BLE operations.