https://devzone.nordicsemi.com/f/nordic-q-a/21538/does-hardware-control-spis-miso-pinI&#39;ve run into some interesting behaviour in my code and wanted to see if anyone can clarify for me. It seems as though the SPIS module doesn&#39;t set the MISO pin as high impedance when the CSN pin is deassertted as the documentation on the infocenter suggestsen-USTelligent Community 13Tue, 25 Apr 2017 06:18:43 GMThttps://devzone.nordicsemi.com/thread/84551?ContentTypeID=1Tue, 25 Apr 2017 06:18:43 GMT137ad170-7792-4731-bb38-c0d22fbe4515:8128b120-f4dc-4611-b1bf-b35e07b3f9d2bjorn-spockeli<p>Happy to help :)</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/84550?ContentTypeID=1Mon, 24 Apr 2017 15:24:01 GMT137ad170-7792-4731-bb38-c0d22fbe4515:bff03d38-7e5b-4de6-9a4a-728ffa1ad09aCorey Bird<p>Fair point. I missed the sentance where it also states &quot;This configuration must be retained in the GPIO for the selected I/Os as long as the SPI slave is to be recognized by an external SPI master&quot;. Thanks for your response!</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/84549?ContentTypeID=1Mon, 24 Apr 2017 13:53:20 GMT137ad170-7792-4731-bb38-c0d22fbe4515:c0947f80-4f28-45ab-8f32-97bc631aebf5bjorn-spockeli<p>Configuring a GPIO pin on the nRF52 to an input with no pull resistor corresponds to a high impedance GPIO pin. My question is why you set the MISO pin as an output after calling <code>nrf_drv_spis_init(...)</code>? The documentation states that <em>To secure correct behavior in the SPI slave, the pins used by the SPI slave must be configured in the GPIO peripheral as described in Table 2 before enabling the SPI slave</em><img src="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/spis_5F00_table_5F00_2.PNG" alt="image description" /></p><div style="clear:both;"></div>