nRF52 reset behaviour on GPIO output pins

RE: nRF52 reset behaviour on GPIO output pins

endnode — Thu, 25 May 2017 11:15:52 GMT

That's what I would suspect: GPIOs might get reset in start-up code before you even enter your main function. Still I would debug this by temporarily redirecting this GPIO to some line which is accessible for logical analyzer/oscilloscope (in the worst case I assume you have P0.21 aka SWD RESET which can be re-purposed as GPIO) and see when exactly line drops to LOW and for how long. If you have another spare GPIO it might be good to use it for signalling where in the code you are (before going to SYSTEM_OFF/after waking up through reset) so you can see when exactly the line get reset (which might indicate if it is in SW - potentially patchable - or if it is HW property of the chip - and so hard to workaround). I'm not and HW engineer but I assume that some capacity might solve this effect (short LOW pulse would still look like HIGH on output)...

RE: nRF52 reset behaviour on GPIO output pins

Eliot Stock — Thu, 25 May 2017 07:06:35 GMT

It's on a development board where I don't have good access to the pin, at least not with all the motion I need to subject the board to in order to get it to wake from sys off, so it's not going to be possible to hook up my logic analyser. But I do have an LED on the board showing the state of the pin and whether the modem has power. If I run gdb and let it break at the top of main, the pin has already gone low by then. None of my code has executed, so it's not something I'm doing in my code that has set it low.

RE: nRF52 reset behaviour on GPIO output pins

endnode — Tue, 23 May 2017 09:31:45 GMT

Any chance to catch the sequence on that GPIO line with fast logical analyzer or oscilloscope? If it realy goes HIGH/LOW/HIGH during wake-up of nRF5x from SYSTEM_OFF then for how long? You can detect this in FW through RESETREAS or GPREGRET registers so then during init sequence of your GPIO output PIN you can avoid certain steps (if they cause change of GPIO line state).