SPIM deterministic TX timing control

RE: SPIM deterministic TX timing control

Jørgen Holmefjord — Mon, 03 Jul 2017 08:03:10 GMT

The reason you see this version as the latest in CMSIS pack installer is that we deprecated support for CMSIS Pack. You can download the no-pack version of the latest SDK from this page. You will find all relevant documentation on our infocenter.

RE: SPIM deterministic TX timing control

kojima — Mon, 03 Jul 2017 00:14:59 GMT

Hi Turbo J,

I got a small progress.

In my older code, I was setting HFCLK after SoftDevice is enabled. ( I have seen CLOCK->HFCLKSTAT.SRC is unexpectedly flipped) Now, I did set HFCLK far before SoftDevice is enabled. Then, the most of the cause of the jitter disappeared.

But, still timing jitter is observed on MOSI pin. When I connect ide debugger ULINK-Pro (but without Periodic Window update disabled), it works fine. But when I let it run stand-alone, only at the very limited duration, jitter appears. Very strange...

RE: SPIM deterministic TX timing control

kojima — Mon, 03 Jul 2017 00:00:03 GMT

Hi Jørgen,

The only reason is ... my MDK-ARM's pack installer suggests it is the latest somehow. Even after executing attached Installer for Keil in nRF5 SDK 13.0.0....

My module mounts Rev.1, not Engineering A/B/C on it.

RE: SPIM deterministic TX timing control

Jørgen Holmefjord — Fri, 30 Jun 2017 10:46:44 GMT

Why are you using S132_nrf52_2.0.0-7.alpha softdevice? Are you using Engineering B revision of nRF52832, where this version is the last one supported?

RE: SPIM deterministic TX timing control

kojima — Fri, 30 Jun 2017 02:40:59 GMT

Hi,

I got another fact that my application is runnig under clock control by SoftDevice.... My target device is nRF52832 and is running on the platform S132_nrf52_2.0.0-7.alpha. My application is a modified one from a sample code of Central-styled UART supplied by Nordic. At somewhere and/or by some reasons, the original sample codes specify this dynamic clock switching behavior. One of the reasons would be poweer-saving... But, In MY case, timing stability is more important than power-saving. So, I suppose, I should patch the code to prevent this before going into deeper analysis. But, I have no enough idea that the SoftDeice S132 does/may-do dynamic HC clock switching right now. Does anyone have suggestions on that ?

RE: SPIM deterministic TX timing control

kojima — Thu, 29 Jun 2017 23:50:39 GMT

Thank you for your suggestion.

But, which errata do you doubt ? I'm driving the chip with HFCLK for stable timing.

Anyway, I tried to kick TASKS_CONSTLAT manually on-the-fly thru the debugger, no behavior change has been obserbed.

RE: SPIM deterministic TX timing control

Turbo J — Thu, 29 Jun 2017 14:58:34 GMT

Have a look at those processor errata. You may want to use the HFCLK or CONSTLAT mode, and maybe disable power save.