GPIO Behaviour During Power Down (NRF52832)

RE: GPIO Behaviour During Power Down (NRF52832)

bjorn-spockeli — Wed, 02 Aug 2017 14:46:50 GMT

Moved to Mypage.

RE: GPIO Behaviour During Power Down (NRF52832)

x_mike — Tue, 01 Aug 2017 16:54:12 GMT

Hi Bjorn,

Thanks for the update.

Regards, Michael

RE: GPIO Behaviour During Power Down (NRF52832)

bjorn-spockeli — Tue, 01 Aug 2017 08:40:42 GMT

Hi x_mike, I am able to reproduce a smiliar behaviour, see the screen shot below

I am unsure why this behavior occurs, but I will investigate and come back to you after discussing this internally.

RE: GPIO Behaviour During Power Down (NRF52832)

Roger Clark — Mon, 31 Jul 2017 22:34:14 GMT

OK.

Shame its still glitching when its in input mode :-(

Hopefully Nordic will be able to give you a software solution.

RE: GPIO Behaviour During Power Down (NRF52832)

x_mike — Mon, 31 Jul 2017 22:16:19 GMT

Thanks, I will create a support request. Wasn't aware of that option.

I have tried setting the pin back to being an input before removing power, but still saw the pulse.

RE: GPIO Behaviour During Power Down (NRF52832)

Roger Clark — Mon, 31 Jul 2017 22:03:58 GMT

Hi Mike

This sounds like something Nordic need to respond to.

I would create a support request via their MyPage system.

PS. My only other thoughts are to potentially fit a FET with less gain ( which is the same package) but that still may not work.

You could potentially also try detecting the power being turned off and put the GPIO into input mode.

Or as you already have a pull down, you could try not setting and clearing the pin, but switch it from output to input mode , as in input mode the pin will be pulled low.

In fact perhaps you should try my last idea first ;-)

Edit.

Looks like you may have already tried it in input mode, but I am not sure...

RE: GPIO Behaviour During Power Down (NRF52832)

x_mike — Mon, 31 Jul 2017 16:53:36 GMT

Hi Roger,

Thanks for looking at this.

Yes exactly, at about Vdd = 0.6V, the GPIO pin suddenly appears to be connected to Vdd. About 0.75 seconds later, after futher decay of Vdd, the GPIO pulls back to GND. This happens on the GPIO where I have a FET connected with a pull down resistor, but it also happens on GPIO pin P0.23, which has nothing connected other than my scope. And oddly it does not happen on P0.24.

I have a pull down on the FET to keep it off by default, even so the pulse is able to turn on the FET. The FET is not fully on, but the circuit driven by the FET is sensitive and responds event to the partial on state of the FET, and yes the FET drives a circuit which remains powered.

I could alter my circuit to deal with the pulse, but this would be a respin of the board layout, so I am hoping there might be a software fix. Perhaps its possible to for instance turn off the power feed to the GPIOs. Probably requires someone at Nordic to take a look, as I haven't seen any published details of internal GPIO driver circuit.

Michael

RE: GPIO Behaviour During Power Down (NRF52832)

Roger Clark — Sun, 30 Jul 2017 10:42:51 GMT

OK.

Its interesting that this only appears to happen on specific pins.

I'm not entirely sure I understand what you are saying.

You seem to be saying that when you remove the power from the nRF52 that the voltage on that pin decays to a specific point and then latches up to the Vdd voltage, which then continues to decay

I'm not sure why this would be an issue, unless you are powering the FET from a different supply which is not turned off, or you are feeding the output of the FET to some other circuit which you are not turning off.

Have you tried pulling the input to the FET low via a 10k or perhaps a 4.7k resistor etc

Does it does this even if the FET is not attached?

RE: GPIO Behaviour During Power Down (NRF52832)

x_mike — Fri, 28 Jul 2017 23:13:30 GMT

Whoops, that would be a good think to mention. I'm using a NRF52832

RE: GPIO Behaviour During Power Down (NRF52832)

Roger Clark — Fri, 28 Jul 2017 22:34:24 GMT

Which MCU are you using? nRF51 or nRF52?