https://devzone.nordicsemi.com/f/nordic-q-a/25461/fstorage-write-erase-and-interruptsnRF52832 SDK14.0 Hi, I had a question regarding the Fstorage Write/Erase operations. My question is what happens when there is an erase or write operation taking place and you get an interrupt? How is it handled? Can you please tell me for bothen-USTelligent Community 13Mon, 03 Jun 2019 00:56:46 GMThttps://devzone.nordicsemi.com/thread/190397?ContentTypeID=1Mon, 03 Jun 2019 00:56:46 GMT137ad170-7792-4731-bb38-c0d22fbe4515:2455a52f-524d-4c93-be52-a7a960c4e985Nandi<p><span>When erasing or writing flash, timer interrupts many times. How can CPU handle this? How can we erase or write flash without losing interrupt</span></p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/100349?ContentTypeID=1Wed, 27 Sep 2017 06:58:23 GMT137ad170-7792-4731-bb38-c0d22fbe4515:eb81010b-81b7-4259-b1fb-47abfb579878Petter Myhre<p>On different interrupt lines? Then they will be handled one after another, according to priority.</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/100348?ContentTypeID=1Tue, 26 Sep 2017 16:23:43 GMT137ad170-7792-4731-bb38-c0d22fbe4515:a01c4892-3896-4434-bad1-97a2053e4af2superpak<p>Thank you, Peter. What if there is more than one interrupt while the CPU is halted during flash erase/write?</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/100347?ContentTypeID=1Tue, 26 Sep 2017 09:09:17 GMT137ad170-7792-4731-bb38-c0d22fbe4515:d9d25b8a-c3e3-4c0a-b9ea-a130afde69f5Petter Myhre<p>The CPU is halted when writing/erasing flash, so the interrupt will be handled after the flash operation is finished. It will be similar, SD also uses NVMC to access flash.</p><div style="clear:both;"></div>