https://devzone.nordicsemi.com/f/nordic-q-a/25552/adding-new-irqn-to-vector-table-on-nrf52-cortex-m4Hi there, I am currently wondering if the following is possible? As stated by the Cortex M4 reference manual states that a system can have 200+ seperate handlers within the vector table. From reading through the NRF52832 datasheet it states thaten-USTelligent Community 13Thu, 28 Sep 2017 12:33:39 GMThttps://devzone.nordicsemi.com/thread/100740?ContentTypeID=1Thu, 28 Sep 2017 12:33:39 GMT137ad170-7792-4731-bb38-c0d22fbe4515:7d8351ff-935c-41d4-b320-6b6506bb9cedRK<p>yes they are for alignment</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/100739?ContentTypeID=1Thu, 28 Sep 2017 12:32:33 GMT137ad170-7792-4731-bb38-c0d22fbe4515:3872cfd1-02f8-4765-bf55-74ae61f3a342jallister<p>What is the point of the &#39;reserved&#39; elements within the vector table at the end? Are they just for alignment?</p> <pre><code> DATA __vector_table DCD sfe(CSTACK) DCD Reset_Handler DCD NMI_Handler DCD HardFault_Handler DCD MemoryManagement_Handler DCD BusFault_Handler DCD UsageFault_Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler DCD DebugMon_Handler DCD 0 ; Reserved DCD PendSV_Handler DCD SysTick_Handler ; External Interrupts DCD POWER_CLOCK_IRQHandler DCD RADIO_IRQHandler DCD UARTE0_UART0_IRQHandler DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler DCD NFCT_IRQHandler DCD GPIOTE_IRQHandler DCD SAADC_IRQHandler DCD TIMER0_IRQHandler DCD TIMER1_IRQHandler DCD TIMER2_IRQHandler DCD RTC0_IRQHandler DCD TEMP_IRQHandler DCD RNG_IRQHandler DCD ECB_IRQHandler DCD CCM_AAR_IRQHandler DCD WDT_IRQHandler DCD RTC1_IRQHandler DCD QDEC_IRQHandler DCD COMP_LPCOMP_IRQHandler DCD SWI0_EGU0_IRQHandler DCD SWI1_EGU1_IRQHandler DCD SWI2_EGU2_IRQHandler DCD SWI3_EGU3_IRQHandler DCD SWI4_EGU4_IRQHandler DCD SWI5_EGU5_IRQHandler DCD TIMER3_IRQHandler DCD TIMER4_IRQHandler DCD PWM0_IRQHandler DCD PDM_IRQHandler DCD 0 ; Reserved DCD 0 ; Reserved DCD MWU_IRQHandler DCD PWM1_IRQHandler DCD PWM2_IRQHandler DCD SPIM2_SPIS2_SPI2_IRQHandler DCD RTC2_IRQHandler DCD I2S_IRQHandler DCD FPU_IRQHandler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved __Vectors_End __Vectors EQU __vector_table __Vectors_Size EQU __Vectors_End - __Vectors </code></pre><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/100741?ContentTypeID=1Thu, 28 Sep 2017 12:06:38 GMT137ad170-7792-4731-bb38-c0d22fbe4515:b7672457-4fee-4222-a428-5663784655feRK<p>No it&#39;s not possible. The number of implemented IRQs is a manufacturer choice, there&#39;s a maximum, the implementer chooses how many to actually implement.</p> <p>If you look at the CPU information in the nRF52 datasheet you will see that 37 vectors are implemented in the NVIC on this chip.</p><div style="clear:both;"></div>