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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>nRF52840 avoid via-in-pad by connecting pins together</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/25750/nrf52840-avoid-via-in-pad-by-connecting-pins-together</link><description>Hi. 
 To avoid via in PAD I like to route a signal/pin from the inner row (closest to center) through a pin in the outer row.
However, to be able to do that I must be sure the pins (GPIO pins) is an input after reset and when programming the device</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 04 Jul 2018 13:25:34 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/25750/nrf52840-avoid-via-in-pad-by-connecting-pins-together" /><item><title>RE: nRF52840 avoid via-in-pad by connecting pins together</title><link>https://devzone.nordicsemi.com/thread/138983?ContentTypeID=1</link><pubDate>Wed, 04 Jul 2018 13:25:34 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:cea5561e-56a8-4709-bc1a-26460dfd34ca</guid><dc:creator>MartinBL</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;The PSELRESET[] registers are a common source of confusion because unfortunately you cannot freely select any GPIO to use as a reset pin. Your only real option is whether to use P0.18 as a reset pin or a regular GPIO. In other words, 18 is the only valid parameter in the &amp;#39;A&amp;#39; field in the PSELRESET register and you can just choose whether you want to use it or not.&lt;/p&gt;
&lt;p&gt;You don&amp;#39;t need the reset pin to program the IC so you don&amp;#39;t need to worry about access to it. When programming and debugging the IC is reset using the SWD lines.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF52840 avoid via-in-pad by connecting pins together</title><link>https://devzone.nordicsemi.com/thread/138870?ContentTypeID=1</link><pubDate>Wed, 04 Jul 2018 03:11:28 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:15069859-253b-48cd-a0c0-f7bea306017b</guid><dc:creator>Patrick Lloyd</dc:creator><description>&lt;p&gt;So I asked a very similar question&amp;nbsp; &lt;a href="https://devzone.nordicsemi.com/f/nordic-q-a/36054/consequences-of-remapping-nrst-on-nrf52840-to-different-pin-to-avoid-via-in-pad"&gt;here&lt;/a&gt;&amp;nbsp;but in response to moving the nRESET pin, I found in the documentation the&amp;nbsp;&lt;a href="http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/power.html?cp=2_0_0_4_2_5_1#unique_1743678815"&gt;PSELRESET[0] and PSELRESET[1]&lt;/a&gt;&amp;nbsp;registers. It means the nRESET pin can be&amp;nbsp;changed to a subset of the available GPIO pins. My concern though was whether or not the reset pin was needed to program a blank SoC. If that&amp;#39;s the case, you run into the problem of needing access to the reset pin to change the reset pin -- defeating the purpose.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF52840 avoid via-in-pad by connecting pins together</title><link>https://devzone.nordicsemi.com/thread/101433?ContentTypeID=1</link><pubDate>Fri, 06 Oct 2017 13:44:04 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:30db4a4b-f97d-4774-a19b-fd2c11d40758</guid><dc:creator>MartinBL</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;Are you aware that the UART traces can be routed to any pins you like and that you can configure the UART in SW to use those pins? You can do this with most peripherals in the nRF5 series, with the exception of the NFC, radio, analog, and debug pins (including the RESET pin). It is a very neat feature that allows you to avoid issues like yours and to avoid crossing traces on your layout.&lt;/p&gt;
&lt;p&gt;&lt;img src="https://devzone.nordicsemi.com/cfs-file/__key/communityserver-discussions-components-files/4/cross.PNG" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;You can&amp;#39;t change the RESET pin though, so then you can do what you suggest. The default reset state of the GPIOs is input mode, but with the input buffer disconnected. So basically they are floating with high impedance. Hence, routing the RESET signal through P0.17 as you suggest, shouldn&amp;#39;t be a problem.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>