nRF52832 P0.09/10 GPIOs

RE: nRF52832 P0.09/10 GPIOs

Jørgen Holmefjord — Wed, 07 Mar 2018 20:30:50 GMT

Unfortunately, the GPIO behavior during reset is undefined and cannot be guaranteed. Is this happening when VDD is very low?

RE: nRF52832 P0.09/10 GPIOs

edwardjpalmer — Wed, 07 Mar 2018 16:49:26 GMT

This is on a custom board. P0.09 is wired directly (i.e. no pullup/down) to the enable line of a load switch, TPS27081. This switch gates power to a cellular modem. Because of the ~2ms high pulse experienced on P0.09 at nRF52832 reset, the modem also tries to power up and the high instantaneous current demand causes a regulator to droop, causing the processor to reset, and this continues endlessly.

P0.10 is wired to UART_CTS of the cellular modem. This isn't powered when the 2ms pulse on P0.09 occurs (since P0.09 being low before the pulse = modem off).

Our solution in this case was to change a capacitor value to considerably increase the turn-on time of the load switch (to beyond 10ms) thus "ignoring" the 2ms enable pulse.

But the cause of the pulse on P0.09 is still a mystery...

RE: nRF52832 P0.09/10 GPIOs

Jørgen Holmefjord — Mon, 30 Oct 2017 12:15:20 GMT

Is this on a custom board or the nRF52-DK? I'm not able to reproduce the issue on the nRF52-DK. Do you see this with any firmware\example from our SDK, or just your project?

RE: nRF52832 P0.09/10 GPIOs

edwardjpalmer — Thu, 26 Oct 2017 18:57:05 GMT

Eric, I had already tried that, with no change to functionality.

Documentation states that if any overvoltage condition is present on P0.09 or P0.10 when configured as NFC, the pins are shorted internally for protection. Knowing this, I also tried setting P0.10 as output and clearing it, but again, that provided no change to functionality.

RE: nRF52832 P0.09/10 GPIOs

Eric Stutzenberger — Thu, 26 Oct 2017 18:32:58 GMT

Hi,

Try clearing the pin first and then configuring it as an output.

nrf_gpio_pin_clear(9);
nrf_gpio_cfg_output(9);

HTH,

Eric