https://devzone.nordicsemi.com/f/nordic-q-a/26394/nrf52-layout-questionsI have been designing a four layer stack up PCB for nrf52832 SoC with chip antenna (2450AT18B100 Johanson Technology). This is the first time I have been designing a PCB with an antenna. I am using kicad EDA Software. The stackup of my design is: en-USTelligent Community 13Tue, 31 Oct 2017 15:52:55 GMThttps://devzone.nordicsemi.com/thread/103865?ContentTypeID=1Tue, 31 Oct 2017 15:52:55 GMT137ad170-7792-4731-bb38-c0d22fbe4515:d69dea77-4630-4f47-ab8a-e1aeb2ee6127Sigurd<p>For layout review and suggestion for &quot;chip antenna ground plane keepout area&quot;, I recommend creating a support ticket at <a href="https://www.nordicsemi.com/eng/nordic/mypage">MyPage</a>. When creating the ticket, please upload your gerber files and schematics.</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/103863?ContentTypeID=1Tue, 31 Oct 2017 14:00:20 GMT137ad170-7792-4731-bb38-c0d22fbe4515:81eacd2e-21ee-4888-bdd6-33930ee6a797abhiarora<p>Thanks a lot for your answers. Can you comment on my other questions? Can you suggest chip antenna ground plane keepout area? Can you suggest something in layout if i am doing it wrong?</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/103862?ContentTypeID=1Tue, 31 Oct 2017 12:28:47 GMT137ad170-7792-4731-bb38-c0d22fbe4515:f420172c-f8de-4455-956e-9a28cbda657dSigurd<p>No, you don&#39;t need to do that. If layer 2 is solid ground plane, you can have what you want in layer 3 and 4.</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/103864?ContentTypeID=1Tue, 31 Oct 2017 09:00:17 GMT137ad170-7792-4731-bb38-c0d22fbe4515:6e34ab15-ffd2-409a-8887-3d44009115b6abhiarora<p>I don&#39;t have keepout in any layer. The layers below CPWG are Layer 2 (Solid ground plane), Layer 3 (3.3V Power layer) and Layer 4 (Bottom Layer which is also solid ground plane). CPWG is on layer 1 which has RF traces and analog signals. Do I need to add keepout under CPWG? i.e., remove layer 3 and layer 4?</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/103861?ContentTypeID=1Tue, 31 Oct 2017 08:18:00 GMT137ad170-7792-4731-bb38-c0d22fbe4515:817bdc58-1087-40f6-84bb-b838c1ee9cecSigurd<p>If the ground plane directly under the CPW line is in layer 2, use the height between layer 1 and layer 2. If the ground plane directly under the CPW line is in layer 4(which would require a keepout in layer 2 and layer 3, under the CPW), you use the height between layer 1 and layer 4.</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/103860?ContentTypeID=1Mon, 30 Oct 2017 15:30:46 GMT137ad170-7792-4731-bb38-c0d22fbe4515:b3efe0ab-90e9-4fb7-bdb9-0af9d533c42cabhiarora<p>Hello, Thanks for replying. Are you sure that I don&#39;t have to consider height from layer 1 to layer 2 (Ground Plane)? You are saying that I have to consider the height from layer 1 to layer 4.</p><div style="clear:both;"></div>https://devzone.nordicsemi.com/thread/103859?ContentTypeID=1Mon, 30 Oct 2017 13:52:55 GMT137ad170-7792-4731-bb38-c0d22fbe4515:726a434e-8641-4c07-9b14-9b416927aeddSigurd<p>Hi,</p> <p>It should not be a problem to use the bottom plane as ground plane in the CPW. You should then use the substrate thickness to the bottom plane when you calculate the trace width and gap to the ground-plane in the top layer. The internal layers should have minimal impact as long as the keepout under the coplanar-trace is wider than the coplanar-trace itself. E.g. &gt; 5x wider</p><div style="clear:both;"></div>