51822 PWM unstable

RE: 51822 PWM unstable

AmbystomaLabs — Tue, 05 Dec 2017 14:52:38 GMT

Or you can switch the code to route your pwm solution out P0.25, P0.24. Those don't have anything connected.

RE: 51822 PWM unstable

AmbystomaLabs — Tue, 05 Dec 2017 14:33:49 GMT

I think you should clarify if you are picking up the signal directly at MUC_PWM or off of Q1_E and Q4_E. You need to remove or bypass all that junk in between. U4 and U5 have huge 2.2mH inductors and a diode output with a 1uF cap. It looks like it was designed to be a boost DC/DC switcher converting Vbat to some higher voltage.

If you are actually ahead (ie, on the base side ) of U4, U5 then not only should you remove the cap but also the series resistance that goes to the base of the transistor.

I don't know what type of project you have in mind, but this is a very poor module to use for it. The module looks like it was designed for a specific application. Normally the modules route the gpio out directly.

RE: 51822 PWM unstable

Blue — Tue, 05 Dec 2017 00:54:23 GMT

The PWM pin is P0.05 and P0.11.

Thanks for your suggestion, I will remove the PWM pin's capacitance and test it.

RE: 51822 PWM unstable

AmbystomaLabs — Mon, 04 Dec 2017 17:26:18 GMT

You should always configure the external crystal if you intend to use it. Some peripheral blocks/drivers will automatically configure it for you but many will run on the HF internal RC which would be a bad idea for pwm. According to the spec the timers run off the whatever the current HF CLK is.

With regard to your board, there will ALWAYS be an external 16MHz crystal. This is because it is required for bluetooth communications. However you still have to configure it otherwise the chip will default to 16MHz RC clk.

Your module has very few direct connections to gpio. In this manner it is COMPLETELY different from the DK. You need to specify which pins you are using since what I see in the schematic is some very aggressive filtering of the gpio output for things labeled "pwm" and the other stuff is designed as "open collector". "open collector" is a rather odd and very outdated choice since BJT's are pretty bad at switched signals when compared to fet's.

RE: 51822 PWM unstable

Blue — Mon, 04 Dec 2017 02:15:36 GMT

Hi, here is the sch pdf, link text
I found that there is an external crystal.

I did not configure HFCLK in the application code, Is there any problem?

The program is working fine on the nrf51 DK board, but not working well on my own board.

RE: 51822 PWM unstable

AmbystomaLabs — Sun, 03 Dec 2017 17:13:56 GMT

Per my question above you should read over page 32 of the nrf51822 spec: 4.2 Timer/counters (TIMER) The timer/counter runs on the high-frequency clock source (HFCLK) and includes a 4 bit (1/2X) prescaler that can divide the HFCLK. The TIMER will start requesting the 1 MHz mode of the HFCLK for values of the prescaler that gives fTIMER less or equal to 1 MHz. If the timer module is the only one requesting the HFCLK, the system will automatically switch to using the 1 MHz mode resulting in a decrease in the current consumption. See the parameters I1v2XO16,1M, I1v2XO32,1M, I1v2RC16,1M in Table 32 on page 47 and ITIMER0/1/2,1M in Table 52 on page 61. The task/event and interrupt features make it possible to use the PPI system for timing and counting tasks between any system peripheral including any GPIO of the device. The PPI system also enables the TIMER task/event features to generate periodic output and PWM signals to any GPIO. The number of input/outputs used at the same time is limited by the number of GPIOTE channels.

RE: 51822 PWM unstable

AmbystomaLabs — Sun, 03 Dec 2017 16:51:33 GMT

There are different levels of power manage. The SD docs discuss these. You can keep the ppi/gpiote running whilst do a power manage.

Still need clarity on HFCLK. Earlier you responded by discussing the LFCLK (ie, RTC). The pclock is generated from the 16MHz clock. You need to make sure it is running on the external crystal and not the internal 16MHz RC clock.

If you feel like posting a pdf of your schematic that would be good too. To make sure there are no mistakes.

RE: 51822 PWM unstable

Blue — Sun, 03 Dec 2017 14:43:47 GMT

Hi, AmbystomaLabs ,

The reason is power_manager () function in while(1), When pwm is working, I need to disable power_manager () function, then pwm works well.

Now the pwm works well on nrf51 DK board, and the time control is very accurate, such as I set the PWM period to 800 ticks(800/16M = 50us)，and set the PWM duty to 20 ticks(20 /16M = 1.25us), I find the PWM works well through the logic analyzer.

But I encountered a new problem on our own board, the PWM duty can not be controlled, it is smaller than the value I set, and the smaller value will be some changes, such as :
I set the PWM duty to 20 ticks(1.25us), In fact, there is no PWM output;
I set the PWM duty to 60 ticks(3.75us), In fact, I find the PWM duty is perhaps 1.5us or greater than 1.5us or less than 1.5us;

Can you help me, What information do I need to provide? Such as PCB?.

RE: 51822 PWM unstable

Blue — Sun, 03 Dec 2017 02:11:57 GMT

3, The process is like this：

power the board , download the program, PWM work properly now.

power off the board, use another 3.3V power supply touch any GPIO pin , and then disconnect.

power the board , this time, PWM work is not normal.

It seems that PWM is very sensitive to electrical interference.

RE: 51822 PWM unstable

Blue — Sun, 03 Dec 2017 02:03:08 GMT

2, I am using sdk 12.3/examples/ble_peripheral/ble_app_uart and using an SD, and my application is not set on clock registers, The application starts, I configure the timer1 like this：

  NRF_TIMER1->PRESCALER = 0;
NRF_TIMER1->MODE = TIMER_MODE_MODE_Timer;
NRF_TIMER1->BITMODE = TIMER_BITMODE_BITMODE_16Bit<<TIMER_BITMODE_BITMODE_Pos;

RE: 51822 PWM unstable

Blue — Sun, 03 Dec 2017 02:02:56 GMT

1, My board does not have an external crystal, I use the internal crystal.

static void ble_stack_init(void) { uint32_t err_code;

nrf_clock_lf_cfg_t clock_lf_cfg = **NRF_CLOCK_LFCLKSRC**;

    // Initialize SoftDevice.
    SOFTDEVICE_HANDLER_INIT(&clock_lf_cfg, NULL);
    ......

}

#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_RC,            \
                                 .rc_ctiv       = 16,                                \
                                 .rc_temp_ctiv  = 2,                                \
                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}

RE: 51822 PWM unstable

AmbystomaLabs — Sat, 02 Dec 2017 17:09:02 GMT

It's not clear from your code if you are requesting (ie, starting HFCLK_EXT). The nRF will always run from internal HFCLK which is not accurate, you have to request HFCLK EXT.

If you are using an SD then you request it through an API command, otherwise you can just set up the clock registers and pclk source.

Also, I assume your comment about powering through gpio port was just a typo, right? You meant just applying vdd from external source.