RE: How to count timer overflows on a synchronized clock?

Audun — Wed, 06 Dec 2017 12:18:14 GMT

Hi Nick,

I'm not sure I fully understand the question, and might need some further background information to understand better if the tip below doesn't make sense.

When a timing packet is received from a peer device the local synchronization timer is reset/cleared slightly ahead of, or slightly after, the wraparound value (2^24 in this case). As you write, this is done by using CC[2] to trigger the TIMER.CLEAR task.

In the synchronization code, a PPI channel is used to trigger TIMER.CLEAR from the CC[2] compare event, and another PPI channel is used to disable the first PPI channel such that it only clears the timer once. Disabling PPI channels via other PPI channels is done using PPI Channel Groups.

In your case, I recommend adding PPI channel 5 to the PPI Channel group which is disabled when CC[2] fires. The behavior should be the following:

A timer packet is received, and an local sync timer adjustment is determined to be required
CC[2] is updated with the adjustment factor
PPI.CHENSET is set to enable all relevant PPI channels, including channel 5 (only update the channel mask value. Adding a second write to the CHENSET register will allow race conditions).
When CC[2] fires the timer will be cleared as normal, PPI channel 5 will cause TIMER4 counter to increment, and then the PPI group containing all relevant channels will be disabled such that CC[2] doesn't continuously trigger this behavior.

Hope this helps!

Audun