nRF52810 Open Drain GPIO

RE: nRF52810 Open Drain GPIO

Gilsaccio — Fri, 15 Dec 2017 15:08:29 GMT

Thank you guys for your prompt and thorough answers, that was exactly what I was looking for. Amazing!

RE: nRF52810 Open Drain GPIO

Jørn — Fri, 15 Dec 2017 15:01:37 GMT

Nothing to be sorry about, the more the merrier :)

RE: nRF52810 Open Drain GPIO

AmbystomaLabs — Fri, 15 Dec 2017 14:46:33 GMT

Sorry I answered too. I think I was looking up the register names when you had already answered it.

RE: nRF52810 Open Drain GPIO

AmbystomaLabs — Fri, 15 Dec 2017 14:26:38 GMT

If you look at the config register settings for the gpio, most pins allow for many settings of RW DRIVE. Quasi open drain or quasi open source are when the corresponding bit status shows "Disconnect". eg, S0D1 is standard open drain with the pull up off for "1".

It should be noted that for anything with a CMOS implementation you cannot pull the gpio higher than Vdd_nRF by Vgs threshold. When this happens the pull up will turn on no matter the state of the register. This is the reason for the max voltage being Vdd+0.3V

RE: nRF52810 Open Drain GPIO

Jørn — Fri, 15 Dec 2017 14:17:38 GMT

Hello Gilsaccio

The closest you get is by configuring the pin to disconnect on logic high, and either be standard or high drive for logic low. This will give the same behavior. In this case, when you set the output level to 1, the pin will go high-Z. When you configure the output to be logic low, the pin will go low and sink current. You can see this explained in this post. However there is a limitation as to how much current you can sink this way, and how high the voltage applied to the pins can be. You can find the absolute maximum rating section here and the electrical specifications for the GPIO here.

Depending on how the sensor behaves when current stops running, the pin voltage, when high-Z, may float up to VCC. Be sure then that does not surpass the absolute maximum rating.

Best regards

Jørn Frøysa