RE: nRF52832 debug

endnode — Thu, 21 Dec 2017 07:25:09 GMT

The question you link is answered and valid for both nRF51 and nRF52 (see registers' description in their respective specifications). Now to your three additional questions (which are not so much related to the first one in fact;):

a) Yes external debugger can access CTRL-AP.

b) From functional point of view it's equal to any other reset mean (e.g. the method you list in point c). If you are interested into very technical details what is sent over SWD (it shouldn't be PIN reset which is different nrfjprog -p command) then this article might give you way how to find it.

c) If you use NVIC_SystemReset() function in your code then (as you can see CMSIS file corresponding to use ARM Cortex architecture) specific value is written to SCB->AIRCR register and then busyloop waits until core resets itself. See e.g. components\toolchain\cmsis\include\core_cm4.h nRF5 SDk file.

Back to your original line: if you want to disable debugging interface (and actually protect the chip against read-back of ROM and RAM and other memory regions during run-time) then you follow the answer there. If you just play with the debugger and you are interested in particular actions there are hopefully some answers here.