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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>nRF52832 and state of I2c during system off</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/28904/nrf52832-and-state-of-i2c-during-system-off</link><description>What are the guaranteed state of the IO lines (configured ax I2c) when in system off mode? Specifically I want another device to be on the bus acting as a master while nRF52832 is off. I’m trying to avoid having to add a buffer. 
 Thanks</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Thu, 04 Jan 2018 12:04:28 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/28904/nrf52832-and-state-of-i2c-during-system-off" /><item><title>RE: nRF52832 and state of I2c during system off</title><link>https://devzone.nordicsemi.com/thread/114380?ContentTypeID=1</link><pubDate>Thu, 04 Jan 2018 12:04:28 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:fbc4272f-5715-40aa-a6cd-545b61a56c20</guid><dc:creator>Stian R&amp;#248;ed Hafskjold</dc:creator><description>&lt;p&gt;Hi, this is described in the TWIM chapter in the PS: &lt;a href="http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52840.ps/twim.html#concept_x2r_gxp_xr"&gt;infocenter.nordicsemi.com/.../twim.html&lt;/a&gt;&lt;/p&gt;
&lt;blockquote&gt;
&lt;p&gt;The PSEL.SCL and PSEL.SDA registers
and their configurations are only used
as long as the TWI master is enabled,
and retained only as long as the
device is in ON mode. When the
peripheral is disabled, the pins will
behave as regular GPIOs, and use the
configuration in their respective OUT
bit field and PIN_CNF[n] register.
PSEL.SCL, PSEL.SDA must only be
configured when the TWI master is
disabled.&lt;/p&gt;
&lt;p&gt;To secure correct signal levels on the
pins used by the TWI master when the
system is in OFF mode, and when the
TWI master is disabled, these pins
must be configured in the GPIO
peripheral as described in Table 1.&lt;/p&gt;
&lt;/blockquote&gt;
&lt;p&gt;So, configured correctly the GPIOs are acting as high impedance input pins in system OFF mode.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>