Main differences between 52810 and 52832?

RE: Main differences between 52810 and 52832?

bjorn-spockeli — Tue, 13 Mar 2018 14:55:27 GMT

Yes, the S112 is production tested on the nRF52832 (hence also the nRF52 DK) with the instruction cache disabled.

RE: Main differences between 52810 and 52832?

butch — Tue, 13 Mar 2018 14:35:01 GMT

Is s112 production tested on the NRF52DK, i.e. as a pca10040e (emulation) project? With or without instruction cache enabled on the NRF52832?

Just to be absolutely clear about how to develop for nRF52810 with s112 using the NRF52DK. Sorry if I have been lax in searching the documents, but I did not see s112 or instruction cache discussed in the Infocenter nrt52810 user guide topic=%2Fcom.nordic.infocenter.sdk5.v14.1.0%2Fnrf52810_user_guide.html

RE: Main differences between 52810 and 52832?

bjorn-spockeli — Mon, 12 Mar 2018 14:29:13 GMT

The DEVELOP_IN_52832 preprocessor define will disable workarounds for erratas that are specific to the nRF52810 and enable workarounds specific for the nRF52832, see the system_nrf52810.c file in one of the pca10040e projects. The Cache is by default disabled on the nRF52832 and must be explicitly enabled in SW, so this should only be an issue if you have enabled it in your pca10040e project. However, you are correct, you could potentially run into race conditions if you develop on the nRF52832 with the cache enabled.

I am afraid that we do not have CoreMark measurements for the nRF52832 with the cache disabled, but I would assume that it is comparable to the nRF52810.

No, the S132 SoftDevice implements workarounds for the erratas for the nRF52832, which may lead to undefined behavior if run on a nRF52810. Also note that the S132 has not been production tested on the nRF52810.

RE: Main differences between 52810 and 52832?

butch — Mon, 12 Mar 2018 13:25:21 GMT

Oh.

So if your code delays using a constant number of instructions (say NOP) then code that works on the nRF52832 might not work on the nRF52810.

If you test on the NRF52DK and disable the instruction cache, does the CoreMark score match the score on a native nRF52810? A developer must ensure that instruction cache is disabled, if they want the timing to match? I don't guess that defining DEVELOP_IN_52832 will ensure the instruction cache is disabled.

Is this timing issue why S132 does not work on the nRF52810? That is, does a Softdevice require instruction cache to be in a certain enable state, and using Softdevice disallow modification of that state while Softdevice is enabled?

RE: Main differences between 52810 and 52832?

bjorn-spockeli — Mon, 12 Mar 2018 08:25:29 GMT

@butch: You are correct. The the cache has been removed on the nRF52810. This will affect the performance of the nrf52810 compared to the nRF52832, but the nRF52810 is more efficient in terms of current consumption as it is a smaller IC(i.e. less peripherals, less memory)

nRF52810
•144 EEMBC CoreMark® score running from flash memory
• 34.4 μA/MHz running from flash memory
• 32.8 μA/MHz running from RAM

nRF52832
• 215 EEMBC CoreMark® score running from flash memory
• 58 μA/MHz running from flash memory
• 51.6 μA/MHz running from RAM

RE: Main differences between 52810 and 52832?

butch — Sun, 11 Mar 2018 16:20:53 GMT

Maybe not a "main" difference, but NVMC has no ICACHECNF register. I can't easily find any discussion. Does this mean the instruction cache exists but is always enabled, or means something else? How does that affect performance/timing?

RE: Main differences between 52810 and 52832?

bjorn-spockeli — Wed, 24 Jan 2018 08:37:43 GMT

@tinyrick: Thanks for the heads-up. Updated my answer.

RE: Main differences between 52810 and 52832?

TinyRick — Wed, 24 Jan 2018 08:24:15 GMT

May also mention that the FPU (Floating Point Unit) is also removed on the nRF52810.

RE: Main differences between 52810 and 52832?

bjorn-spockeli — Wed, 07 Jun 2017 11:00:23 GMT

The main differences between the nRF52810 and the nRF52832 are the following

NFC peripheral has been removed on the nRF52810
Flash reduced from 256kB to 192kB and RAM reduced from 32kB to 24kB.
Number of SPI/TWI Master peripherals reduced from 3 to 2 ( 1 x SPI Master or Slave + 1 x TWI Master or Slave)
Number of PWM channels reduced from 12 to 4.
I2S Peripheral has been removed.
Low Power Comparator has been removed
Number of 32-bit 16MHz Timers reduced from 5 to 3
Number of 32.768kHz RTCs reduced from 3 to 2.
The number of GPIOTE channels reduced from 8 to 4.
FPU (Floating Point Unit) removed.
Cache removed