Altering QSPI Address Mode?

RE: Altering QSPI Address Mode?

Mickael — Fri, 12 Jan 2018 15:35:57 GMT

Hi Hung Bui,

Do you know if thar QSPI limitations has been planned to be solved in the coming new silicon release? Supporting MICRON NAND Serial Flash would surely be a very big plus for the MCU...

Thanks for the help, Mickael

RE: Altering QSPI Address Mode?

Fan Jiaming — Tue, 27 Jun 2017 09:04:52 GMT

Hi. I am thinking of using normal SPI as well, as least I will be able to read/write normally. Thanks for your help!

RE: Altering QSPI Address Mode?

Hung Bui — Tue, 27 Jun 2017 08:40:43 GMT

Hi Fan,

I afraid it's not possible with QSPI to talk to the Flash. Here is a quote from our developer: "My initial idea was to shift the address to the left by 8 bits and make the unused least significant byte the dummy byte. However, we cannot configure our IP with zero dummy bytes."

What you can do is to use normal SPI to you have full control of what should be transmitted. We may have more improvement with QSPI in our production version of nRF52840 but it's not ready yet.

RE: Altering QSPI Address Mode?

Fan Jiaming — Mon, 26 Jun 2017 14:01:13 GMT

To add on, the onboard flash is capable of using 24 bits for the addressing, such as section 10-12, 10-14, 10-22, 10-23 in the datasheet: www.macronix.com/.../MX25R6435F, Wide Range, 64Mb, v1.4.pdf Although this is NOR and mine is NAND, I am not very sure does this means there is a difference in the NOR and NAND addressing schemes.

RE: Altering QSPI Address Mode?

Fan Jiaming — Mon, 26 Jun 2017 13:44:03 GMT

I wanted to use multiple IO lines for read and write, after I post the question, I realize the difference in addressing scheme affects both the operations. For example Figure 13 and Figure 14 in the datasheet shows the addressing scheme using 16 bits. As for the write, Figure 16 also shows that (This 1Gb chip does not support more than one IO line for write, but for the one I am using, it has an additional write mode that uses 4 data lines to send data, which is the picture in my original question). But the problem is that the difference in the 24 bits and 16 bits addressing means I would loss data when reading and transfer wrong data when writing. To be more clear, for read, there is a work around in the chip that I am using but is not shown in the datasheet that I pasted (I am sorry for that), but the write has this addressing issue that I total cannot write correctly to the chip.

RE: Altering QSPI Address Mode?

Hung Bui — Mon, 26 Jun 2017 13:22:36 GMT

Hi Fan,

Could you point me to the figure/description showing the difference in addressing scheme in the new datasheet ? Now you are concerning write command not read command ?

RE: Altering QSPI Address Mode?

Fan Jiaming — Mon, 26 Jun 2017 11:24:50 GMT

Hi, the datasheet actually require login in order to retrieve it from the Micron website. However, I manage to find a similar chip that has open access link. It differs from the chip that I am currently using but the addressing scheme is the same. Link: datasheet.octopart.com/MT29F1G01AAADDH4-IT:D-Micron-datasheet-11572380.pdf My main problem is that the chip has write issue because the address is 16 bits. (13 + 3 dummy bits, sorry for the error in the question)

RE: Altering QSPI Address Mode?

Hung Bui — Mon, 26 Jun 2017 09:27:08 GMT

Hi Fan,

Could you please provide the datasheet of the NAND flash ?