RE: nRF24L01+ timing diagram

Vito — Thu, 03 Jul 2014 09:32:52 GMT

Hello, thanks for your answer. I will scope carefully the CE pin then.

The delay that you are measuring is off due to the logic that fires up the radio (setting CE and waiting for IRQ to assert).

From what you say, I understand that the code inside the nRF24l01+ can take a different amount of 16Mhz clock cycles, in order to poll CE and to set IRQ. However in your calculation you did not not include the Tirq time of 4us which is what makes my measurement so far from the calculation.

Is it the same on the RX side? Is it true that if do an adequate number of measurements I can probably spot the "lowest execution time"? Or are there some numbers, like what are the minimum and maximum execution times for TX and RX, in addition to the 154us you calculated? Thanks again, best regards

Vito

RE: nRF24L01+ timing diagram

Håkon Alseth — Thu, 03 Jul 2014 08:05:00 GMT

Hi,

The timing of the transmitter is set as according to our specification and will not vary. The PLL start up time will be 130 us (Tstdby2a), and each bit will be 0.5 us in 2 MBit mode. Using 3 byte address, one byte payload, one byte CRC; this will give you a total time of:

130 us + (1 byte Preample + 3b address + 1 b payload + 1 b CRC)*8/ 2MBIT = 130 + 24 us = 154 us.

The delay that you are measuring is off due to the logic that fires up the radio (setting CE and waiting for IRQ to assert). You should hold the CE pin active for at least 10 us to be certain that the radio starts up. If you have a lot of capacitance on this pin, you will see a slope before reaching a logical defined level '1', which is one of the reasons that we recommend this timing on the CE pin.

The jitter of all clock operations are directly derived from the 16M xtal. Meaning that the 2.4 GHz signal will have the same jitter as your clock source (lets say; 40 ppm including aging and temperature tolerance)

Best regards, Håkon