NRF52 current peaks

RE: NRF52 current peaks

MartinBL — Wed, 31 Jan 2018 10:03:33 GMT

Great! Please keep us posted.

RE: NRF52 current peaks

genis — Wed, 31 Jan 2018 09:54:15 GMT

Sorry for the late response. I'll see if I can test different decoupling capacitors and see what effect has on the refresh mode.

RE: NRF52 current peaks

MartinBL — Fri, 26 Jan 2018 12:34:33 GMT

I had a chat with our current measurement guru, and it is indeed possible that it's just the refresh mode you are seeing. The height, frequency, and pulse width of the current spikes that is caused by the refresh mode depends on:

The current drawn by the nRF52. Higher current consumption -> more frequent pulses.
The size of your decoupling capacitors. Larger capacitances -> wider spikes.
The internal resistance of your decoupling capacitors. High resistance -> wider spikes.
The internal resistance of your power supply. Low resistance -> high spikes.

If you had an ideal power supply (without internal resistance) and ideal decoupling capacitors (also without internal resistance) your current spikes would be infinitely high and infinitely narrow.

So while your spikes are in the high end of what we usually see, the periodicity of them is a strong indicator of this being the refresh mode in action.

RE: NRF52 current peaks

genis — Fri, 26 Jan 2018 09:46:52 GMT

Yes, I saw the same behaviour on larger projects. I didn't try on the nRF52 demo board so it's probably worth trying it and see if there's the same beaviour. Is there anyway to lower the amplitude of the spikes? Are they affected somehow by any components around the chip?

RE: NRF52 current peaks

MartinBL — Thu, 25 Jan 2018 13:24:55 GMT

If you saw the same spikes in other projects I suppose you have done it correctly, but I'm going to ask anyway: does your probe attenuation match the settings on your scope? 13-14mA is suspiciously close to 10x of what you would expect from the refresh mode. The frequency seems a bit high for refresh in system off though, but the pulse width (10-15uS expected) seems to match too.

RE: NRF52 current peaks

genis — Thu, 25 Jan 2018 08:25:27 GMT

Thank you for your help. That's the only code in my project apart from the startup code, which I got from one of the examples in the SDK. The chip is powered at 3V and supply is stable and no reset is occurring.

I saw the same spikes while monitoring the consumption in a larger project. I started to remove code modules to try to identify what was causing the current spikes and ended up with the snippet I pasted no the question. In the original, larger project I could see the same kind of spikes although at a different rate.

The behavior I see is very similar to the "power off" graph in this tutorial: devzone.nordicsemi.com/.../. The biggest difference is that my current spikes are way larger than those in the tutorial. I wonder if I could reduce them somehow as it's drawing a lot of power from the battery right now.

RE: NRF52 current peaks

AmbystomaLabs — Wed, 24 Jan 2018 17:19:36 GMT

The RF events are certainly the peak power times, however even during constant use of the processor the SD (when used) will switch to the DCDC since power consumption is improved dramatically.

Even so, the DCDC runs at probably 1MHz or more (the spec doesn't say) and definitely not at 3.5Hz. And, since DCC is on for either LDO or DCDC operation, it is not like there should be a large spike to fill up caps or something.

If that is really all the code on the device then all GPIO should be in input mode and not sourcing. I would suggest you put in the code some way to make sure it is not resetting at 3.5Hz. You could have local noise driving the reset line. And, you should monitor vdd_nRF to make sure there isn't a corresponding dip that is causing a brownout reset.

What voltage are you running the nRF at?

RE: NRF52 current peaks

genis — Wed, 24 Jan 2018 16:58:13 GMT

Ok, I read somehwere that the DC/DC basically activates on RF operation. And I disconnect the SWD after I flash it.

RE: NRF52 current peaks

AmbystomaLabs — Wed, 24 Jan 2018 16:40:44 GMT

The DC/DC will run in the megahertz range and should only come on during major IC activity. Otherwise it just uses the LDO which has a high frequency white noise pattern and very small amplitude.

You are disconnecting the SWD when running this test, right?